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Low Power Problem
Designers today face a challenging set of conflicting priorities: Reduce power and cost while increasing performance and functionality. The advanced low power design techniques now required force a major shift in how engineers create and verify chips. These techniques can dramatically reduce power consumption in deep submicron chips but have traditionally required ad-hoc, time-consuming, risk-prone, and manual verification and implementation approaches.
Eclypse Low Power Solution
The Eclypse™ Low Power Solution simplifies advanced low power design and verification by combining and automating a wide array of advanced techniques, methodologies, and standards. Building on more than 10 years of low power design leadership, the Eclypse Low Power Solution delivers leading-edge, silicon proven, advanced low power technologies.
The Eclypse Low Power Solution supports the industry-standard Unified Power Format (UPF) language, which is used to capture low power design requirements. The following UPF-enabled tools are included: MVRC™ and VCS® with MVSIM™, key components of the Discovery™ Verification Platform, and Design Compiler®, Power Compiler™, IC Compiler™, DFT MAX™, Formality®, and PrimeTime®, key components of the Galaxy™ Design Platform. Completing the solution are additional tools for low power design, including Innovator™, HSPICE®, HSIM®, NanoSim®, TetraMAX®, and PrimeRail™, as well as DesignWare® IP and Synopsys Professional Services. The Eclypse Low Power Solution supports open methodologies, including those described in the "Low Power Methodology Manual" (LPMM), co-authored by Synopsys and ARM.
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