How to Drastically Enhance Analog Layout Efficiency Using a Highly Reusable User-Defined Device

One clever presentation I heard recently was from Endura Technologies at this year’s SNUG. They gave a presentation called “Radically Improving Layout Efficiency through the Use of User-Defined Devices (UDD)”. They highlighted how they love the intuitive nature of Custom Compiler’s visually-assisted layout automation and used its powerful capabilities for their embedded power management IC (PMIC) designs. The team developed highly reusable and programmable complex layout blocks on various technology nodes and said they achieved a 2X reduction in effort compared to their previous technique.

The key Custom Compiler feature they used to achieve the improved productivity is called UDD. Let me tell you more about it.

But PDKs don’t provide the specific variants (e.g., layout only cells – TAPs, DeCaps, fillers and guard rings). Also, layout designers often create custom structures around PDK PCell (e.g., creating customized routes for easy connections or extendable power/ground (PG) mesh that can be used per instance). All of these customized layout structures take time to build and often not reusable without extra effort.

Historically, programming language expertise has been required to create complex PCells that function reliably and efficiently. Simple GUI-based tools for PCell creation have been available, but the usage was constrained to very simple structures and the solution was not scalable with increased complexity.

The principle behind PCells can be extended to generate common analog building blocks for the same benefits of efficiency, uniformity, and ease of maintenance.

Custom Compiler UDD is a graphical environment for PCell generation by layout designers within their familiar layout environment. There is no need for programming, and the users intuitively create the complex programmable layout structures just like they have been creating custom layout.