HELPING YOU DESIGN THE CHIP INSIDE
Products and Solutions
---------- SOLUTIONS ----------
Eclypse Low Power Solution
Galaxy Design Platform
Design for Low Power
Design for Test
Design for Yield
RTL Synthesis
Physical Implementation
Sign-Off
Liberty CCS
SDC
Milkyway
Discovery Verification Platform
Analysis and Debug Tools
Low-Power Verification
System Analysis & Design
Smart RTL Verification
Functional Equivalence Checking
Mixed-Signal
Languages
Intellectual Property (IP)
DesignWare Library
DesignWare Verification IP
DesignWare Cores
DesignWare Star IP
DesignWare Foundry Libraries
IP Reuse Tools
Design for Manufacturing
Design-Yield Analysis
Mask Synthesis
Mask Data Preparation
Lithography Verification
TCAD
Manufacturing Yield Management
Professional Services
Tool and Methodology Deployment
Pilot Design Environment
Flow Optimization
Implementation
Verification Consulting
Concept to Parts
Core Hardening
---------- PRODUCTS ----------
BSD Compiler: Test synthesis
Cadabra: Cell creation
Calibration Library
CATS: Mask data preparation
Circuit Explorer: Analysis & Optimization
coreAssembler
coreBuilder
coreConsultant
CosmosLE: Layout design environment
CosmosScope: Waveform analysis
CosmosSE: Schem. design environment
DC Ultra: RTL synthesis
Design Analyzer: RTL synthesis
Design Compiler: RTL synthesis
DesignWare: Design & verif. IP
DesignWare Virtual Platforms
DFT Compiler MAX
DFT Compiler: Test synthesis
DSSA Sentry
Enterprise: Layout editor
ESP: Transistor-level Equivalence Checking
Formality: Funct. equiv. checking
Hercules: Physical verification
HSIM
HSPICE: Accurate circuit simulation
IC Compiler
IC Workbench
Innovator: SoC / system modeling
JupiterXT: Design planning
Leda: RTL checker
Library Compiler: Library compilation
Liberty NCX: CCS Characterization
Magellan: RTL formal verification
Memory Solution
Milkyway: Design database
MVRC
MVSIM
NanoChar: 90 nanometer & below characterization
NanoSim: Fast circuit simulation
NanoTime
Odyssey Defect/Odyssey YMS
Paramos
Pilot Design Environment
Pioneer-NTB: SystemVerilog testbench automation
Power Compiler: Power optimization
PrimePower: Power analysis
PrimeRail
PrimeTime PX
PrimeTime: Static timing analysis
PrimeTime SI: Signal integrity analysis
PrimeYield Tool Suite
Proteus OPC
PSM-Create & PSM-Check
Raphael
Raphael NXT
Recipe Manager and Editor (RME)
Saber: Multi-tech. simulation
Scirocco: VHDL simulation
Seismos
Sentaurus Device
Sentaurus Lithography
Sentaurus Process
Sentaurus Structure Editor
Sentaurus TFM
Sentaurus Topography
Sentaurus Workbench
SiVL-LRC: Lithography verification
SpiceCheck
SpiceExplorer
Star-RCXT: Full-chip RC extraction
Star-RCXT VX
Star-SimXT: Fast circuit simulation
System Studio: DSP algorithm design
Taurus-Medici
Taurus-TSuprem4
TetraMAX: ATPG
VCS: Comprehensive RTL Verification
VCS MX: Mixed-HDL simulation
Vera: Testbench automation
WaveView Analyzer
DESIGN IMPLEMENTATION
VERIFICATION
INTELLECTUAL PROPERTY
DFM/TCAD
DESIGN SERVICES
VMM CATALYST PROGRAM
MEMBERS
BECOMING A MEMBER
NEWS AND ARTICLES
INFORMATION ABOUT VMM
VMM Catalyst Program Members
Aldec
Ammos Software Technologies
ARM
Avery Design Systems
Blue Pearl Software
Bluespec
Callidus Systems
Calypto
Certess
Chipright
ComputerBasedEducation
Contemporary Verification Consultants
Denali
Doulos
eInfochips
Esterel Technologies
EVE
ForteLink Inc.
HCL
Ingot Systems
Innovative Logic
IntelliProp, Inc
Interra Systems
Intrinsix
IPextreme
JEDA Technologies
Kacper Technologies Pvt Ltd
Krispan
Masamb Electronics Systems
MindTree Consulting
NoBug
Novas Software
nSys Design Systems
Paradigm Works
Patni
Perfectus Technology
Persistent Systems
Productivity Design Tools
Rainbow Cyclone
Real Intent
Silicon Interfaces
Silicomotive Solutions
SONAC
Sunburst Design
Sutherland HDL
Synplicity
Tes Electronic Solutions
TooMuch Semiconductor
TransEDA
Trustic
UV-Tech Consulting & Training
VeriEZ Solutions
Verific Design Automation
Verification Central
Verifore Inc.
Verilab
VeriSure Digital
Willamette HDL
Wipro Technologies
XtremeEDA Corporation
Zocalo Tech, Inc.
CONTACT US
|
FEEDBACK
|
LOCATIONS
|
PRIVACY POLICY
|
LEGAL
© 2008 Synopsys, Inc. All Rights Reserved.