|
The Signal Integrity Sign-off Solution
|
|
Overview
With the advent of shrinking process geometries and rising clock frequencies for nanometer
designs, signal integrity (SI) effects such as crosstalk delay and noise (or glitch) propagation
can cause functional failures or failed timing. It is essential for designers to address these SI
problems to ensure that their designs are delivered to market correctly in the shortest amount
of time. Time-to-market pressure, chip complexity, and control of SI effects are all factors requiring
an accurate, fast, and trusted analysis and sign-off solution. The Synopsys PrimeTime SI solution
builds upon the trusted PrimeTime solution to accurately and quickly analyze signal integrity effects.
Figure 1: Galaxy Sign-off Solutions
The Challenge
At 130-nanometers (nm) and below, signal integrity effects, such
as crosstalk between signals caused by capacitive coupling,
became mainstream design challenges. Without adequate
attention, these effects will result in performance degradation,
functional failure, or reliability problems. Signal integrity effects
are interdependent with timing and need to be analyzed in the
context of timing. This tight loop and interdependency requires
an integrated approach for signal integrity and timing analysis.
The PrimeTime SI solution delivers an efficient, accurate and
unified environment to analyze signal integrity effects.
Figure 3: Crosstalk Delay Analysis Pinpoints
Crosstalk Timing Failures
The Solution
The Synopsys PrimeTime SI solution is a full-chip, gatelevel
signal integrity analysis and sign-off tool integrated
within the Synopsys Galaxy™ Design Platform. It accurately
analyzes crosstalk delay, noise (glitch) and IR drop within the
tape-out proven PrimeTime static timing analysis and signoff
environment. Combined with industry-leading runtime
performance and capacity, the PrimeTime SI solution enables
designers to achieve first-pass silicon success and fast time-tomarket
on their multimillion-gate designs.
Key Features and Benefits
Comprehensive and efficient SI analysis built-into the PrimeTime environment
The unified approach of signal integrity and timing analysis
delivers a comprehensive and time-efficient method to concurrently
analyze noise and crosstalk delay effects on timing.
Additionally, the concurrent analysis in a single tool enables
faster results while improving designer productivity.
Accurate crosstalk delay, noise (glitch) and IR drop analysis
Signal integrity effects are interdependent and need to be
analyzed in the context of timing. PrimeTime SI uses an
integrated golden delay calculation engine with the proven and
trusted PrimeTime static timing analysis engine to accurately
model and compute timing deviations due to crosstalk and IR
drop. PrimeTime SI also performs accurate noise calculation,
detection, and propagation on large designs.
Figure 4: Crosstalk Noise Analysis Pinpoints Functional Crosstalk Failures
Ease of adoption and use
PrimeTime SI, an extension of PrimeTime Static Timing Analysis
(STA), is easy to use and adopt. It utilizes the familiar PrimeTime
flow and environment, with the same commands, user interface,
reports, and attributes.
Figure 2: PrimeTime SI Flow—Easy to
Use and Adopt
Industry-leading performance and capacity
PrimeTime SI is based on the proven Synopsys static timing
analysis technology. It provides the capacity required to analyze
multimillion gate designs and the performance needed to
minimize run times at the full-chip level.
- Additional Features
- Reduces false violations by considering slew propagation, timing windows, and logical correlation of signals
- Hierarchical SI analysis capabilities using ILMs with crosstalk
- What-if analysis
- Distributed multi-scenario analysis
- Path-specific analysis
- Save and restore
- Adaptive waveform propagation
- Unified Power Format (UPF) support
- Multi-voltage support
- SPICE deck output
- Supports industry-standard Non-Linear Delay Model (NLDM) and Composite Current source (CCS) noise libraries
- Includes fast CCS noise library characterization utility
- Integrated within the Synopsys Galaxy Design Platform, enabling rapid SI closure
About the Galaxy Design Platform
The Galaxy Design Platform is an open, integrated design
implementation platform with best-in class tools and IP,
enabling advanced semiconductor design. Anchored by
Synopsys’ industry-leading semiconductor design tools and
the open Milkyway™ database, the Galaxy Design Platform
incorporates consistent timing, SI analysis, common libraries,
delay calculation, constraints, testability, and physical verification
to provide a convergent flow from RTL all the way to
silicon. The Galaxy Design Platform helps reduce design time,
decrease integration costs and minimize the risks inherent in
advanced, complex semiconductor design.
|
