Open Environment for IP-Based Subsystem Design
Overview
The DesignWare® coreAssembler product is part of the complete set of IP reuse tools available from Synopsys. coreAssembler provides a graphical or command-based environment that guides the designer through the assembly and configuration of an IP-based subsystem. With coreAssembler, designers can easily generate the configured RTL of a subsystem based on the AMBA IP from the DesignWare Library or from IP with an interface that has been packaged for use with coreAssembler.
With coreAssembler, you can also easily create and package the complete IP-based subsystem for reuse.
- Features
- Intuitive graphical or script-based environment
- Guides the IP integrator through the assembly of an IP-based subsystem
- Guides the IP integrator through the configuration of the components contained in the subsystem
- Generates the RTL configuration and interconnect logic
- Supports subsystem packaging
- Includes built-in interfaces to Synopsys tools including:
- Design Compiler™
- Physical Compiler™
- Power Compiler™
- DC FPGA
- PrimeTime®
- Formality®
- VCS™
- TetraMAX®
- Flexible TCL interface for tool customization
- Supports multi-language designs
- Supports the import of unpackaged IP
- Benefits
- Reduces SoC development costs by automatically generating configured subsystems
- Reduces IP integration costs by speeding time to verification
- Reduces script maintenance costs with built-in interfaces to Synopsys tools
 Datasheet
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