DesignWare® Low Power IP by Design

Overview
Low power management is a critical design challenge for many of today's systems-on-chips (SoC). Engineers are often faced with the challenge of creating complex SoCs with increased amounts of functionality while maintaining or decreasing power consumption. Adopting reusable IP has become a common practice to help cope with the increased design complexity while maintaining time to market schedules. With this mind, designers who are implementing a chip level power strategy must now taking into consideration the IP vendor's ability to provide IP that is designed with low power techniques and can be easily integrated into the chip.

As a leader in low power IP, DesignWare® IP supports a wide range of low power features such as configurable shutdown and power modes. An integral part of the Synopsys Eclypse low power solution, the DesignWare digital IP is designed to support low power methodologies and the PHY IP consumes up to 50% less power than the competition. As a leading IP provider, Synopsys offers a broad portfolio of IP that is low power by design.

DesignWare PHY IP
Synopsys' comprehensive portfolio of high performance, low power mixed-signal PHY IP for the PCI Express, SATA, XAUI and USB protocols, enable designers to quickly integrate high performance interfaces into their next-generation SoCs while minimizing power consumption. Designed with low power in mind, all of the DesignWare PHY IP is built with a high performance architecture that provides low area and up to half the power compared to competitive solutions.

The Synopsys DesignWare USB IP now provides support for the USB 2.0 Link Power Management (LPM) and High Speed Inter-Chip (HSIC) standards. The DesignWare USB LPM and HSIC IP reduces power consumption and area for USB-enabled designs. LPM defines a new sleep state to provide faster suspend and resume times and HSIC eliminates the USB connectors and cables, thus simplifying the USB connection down to two wires.

DesignWare Digital IP and Foundry Libraries
Synopsys' DesignWare digital IP portfolio support a wide range of protocols such as PCI Express®, USB and DDR. The low power digital IP when combined with the PHY IP and Verification IP provide designers with an integrated, complete IP solution. The DesignWare digital IP leverages Synopsys. low power design tools and methodology to enable more power efficient integrated circuits. Maximum extent of the digital cores can be clock gated to reduce power. In addition, it also supports low power management schemes specified by the protocol standards.

Synopsys also provides DesignWare Foundry Libraries, which, by partnering with industry leading foundries, such as TSMC and Chartered, provide easily accessible, silicon-proven standard cells, I/Os and memories, all of which are optimized for their process technologies.

• Low Power Design for Analog/Mixed-Signal IP

• Complete DesignWare IP for PCI Express Helps Reduce Power Consumption and Lowers Area for Ralink Chipset
• High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity
• Combination of Tools, IP and Services Help Teradici Achieve First Silicon Success
• High Quality DesignWare IP for PCI Express Helps SiCortex Enable First Pass Silicon Success
• Silicon-Proven DesignWare USB 2.0 PHY IP Lowers Risk and Enables First Pass Silicon Success for Hisilicon Technologies
• Proven DesignWare IP for PCI Express Reduces Integration Risk and Speeds Time-to-Market for Stretch
• High Quality IP Saves Open-Silicon Three Months on Schedule

• Low Power USB 2.0 PHY IP for High-Volume Consumer Applications
• Solving the Integration Challenges for USB-Enabled Designs
• Implementing Physical Layer Connectivity in Deep Sub-Micron Technologies