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Overview
Synopsys provides engineers with the broadest portfolio of Verification IP for the industry's most popular bus protocols including AMBA 3 AXI, AMBA 2.0, PCI Express, USB 2.0 OTG, Ethernet, Serial ATA and thousands of memory models.
DesignWare Verification IP integrates easily into Verilog, SystemVerilog, VHDL and OpenVera testbenches to generate bus traffic and check for protocol violations. Monitors provide extensive reports to show functional coverage of the bus protocols.
DesignWare Verification IP provides an easy to use command interface for the industry's commonly used simulators including Synopsys VCS, Mentor Graphics ModelSim and Cadence NC-Sim.
Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
The Verification Methodology Manual for SystemVerilog, co-authored by Synopsys and ARM, defines a coverage-driven, constrained random methodology that speeds time to reach coverage goals.
DesignWare Verification IP provides extensive support for the VMM and includes scenario generators and transactors to significantly reduce testbench development time.
Verification IP and Native Testbench
For high performance verification, DesignWare Verification IP supports VCS Native Testbench (NTB) technology. VCS compiles the Verification IP natively to provide up to five times faster runtime performance.
DesignWare Verification IP also supports Pioneer NTB, Synopsys testbench automation tool, to give high performance in ModelSim and NC-Sim simulation environments.
VCS Verification Library
The VCS Verification Library is the industry's broadest portfolio of standards-based verification IP which integrates easily into Verilog,
SystemVerilog, OpenVera and VHDL testbenches to generate and respond to bus traffic, check for protocol violations, and generate coverage reports.
The VCS Verification Library supports the Verification Methodology Manual (VMM) for SystemVerilog using Synopsys' Reference Verification Methodology (RVM).
Support for Native Testbench in VCS provides up to 5X improvement in runtime performance.
Key Benefits
- Broadest verification IP portfolio in the industry
- Delivers 5X simulation performance improvement with VCS
- Supports proven verification methodology for SystemVerilog
- Includes example testbenches to accelerate learning and speed testbench development
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