Overview
Design Compiler® in the Galaxy™ Design Platform is the industry's most comprehensive and production-proven suite of RTL synthesis and test solutions. Its premier synthesis product, DC Ultra, shares topographical technology with the IC Compiler physical implementation solution to enable designers to accurately predict post-layout timing, power and area during RTL synthesis without the need for wireload model-based timing approximations. The tight correlation between synthesis and physical implementation significantly reduces costly and time-consuming design iterations.
»Play Video 04:38
|
|
Perspective: Boost your design productivity
Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule. Hear what Antun Domic, senior vice president and general manager of Synopsys' Implementation Group, has to say about this new breakthrough in design automation.
|
The latest addition to the product family is Design Compiler Graphical, a tool that further extends DC Ultra topographical technology to help RTL designers predict, visualize and alleviate wire-routing congestion early in the design flow, prior to physical implementation. By helping designers avoid congestion problems before they occur, Design Compiler Graphical can significantly lower project time, effort and cost.
The award-winning Synopsys test solution is built into Design Compiler and offers designers the fastest and most cost-effective path to high-quality manufacturing tests and working silicon. The Design Compiler family also includes Power Compiler™ for power optimization and automation of advanced power management techniques. Completing the solution are the Formality® equivalence checker and the DesignWare® library with its unequalled variety of IP. These best-in-class, production-proven solutions are integrated to achieve the industry’s fastest and most predictable RTL-to-GDSII flow.
- Key Benefits
- Tight timing, area, and power correlation with physical implementation
- Congestion prediction and visualization with Design Compiler Graphical
- Synthesis optimizations to mitigate congestion "hot spots" with Design Compiler Graphical
- Best-in-class timing, area, and power QoR with DC Ultra
- Tight correlation with PrimeTime, the industry's standard for timing sign-off
- Highest testability at lowest test cost with Galaxy test solutions
- Lowest power with most advanced power management solution, Power Compiler
- Seamless formal verification with Formality
- Access to the industry's largest IP repository with DesignWare
Back to Galaxy Design Platform
|
