Techniques in Verification of Mixed-Signal and SoC Designs using NanoSim By Sandeep Mehndiratta, Sr. Technical Marketing Manager

Introduction
Shrinking process geometries, higher frequencies and increasing design complexity are stretching the limits of design tools and methodologies. Recent advances in silicon technology have made it possible to design with significantly larger gate densities and higher clock frequencies. Design engineers have usedthese advances to integrate more complex functionality into their system-on-chip (SoC) designs. As process geometries move into the nanometer range, even digital logic circuits start behaving like analog circuits, and for these high-performance designs, cell-based verification flows are insufficient; designers need to move to custom designs for accurate simulation of transistor level effects.

These trends have led to some significant challenges in the area of verification:

• Convergence of custom and cell-based flows without any integration of verification methodologies
• Need for early integration verification in the full chip context to ensure functionality compliance
• Longer verification cycles for designs with equally large digital and analog blocks (“Big D, Big A”)
• Integration of larger custom analog circuits with standard CMOS logic in hard macros
• Avoiding design errors due to complex analog and digital interfaces that may affect function and timing

In this paper, we’ll illustrate how NanoSim, the market leader in high-performance circuit simulation, has evolved into the most comprehensive solution for verification of mixed-signal designs and SoCs.

Mixed-Signal Verification Flows Today
Traditionally, different teams verify the digital and analog components of a design. Digital parts of the design are verified in a synthesis/HDL environment, and the analog components in a circuit simulation environment. But, with these teams working independent of each other, there is no full-chip integration verification of the mixed-signal SoC. Any integration issues are accounted for by making assumptions in the test benches and by providing sufficient guard-banding around the analog block to isolate digital noise from the sensitive analog substrate. However, with more complex functionality integrated on the chip and increasing on-chip clock frequencies, guard-banding is no longer an option because it cannot account for the functionality embedded within the analog blocks. Additionally, it is not practical to waste silicon/die space when not necessary, as it adds additional fabrication expense down the road.

Another common approach for verification of mixed-signal designs in the full chip context has been to use digital HDLs for modeling the behavior of analog blocks. These models are limited in their effectiveness because they are not able to mimic all analog behavior and there is no way of correlating the HDL model against the true functionality of the analog block. Results from such simulations are dubious at best, since actual circuit parameters determined by parasitic extraction cannot be reliably annotated into the HDL behavioral.

A more successful verification flow is to simulate the entire chip at the transistor level. This needs a complete transistor-level representation of the design, and hence is possible only at the end of the design cycle, when all cell and custom components have been completed. With the high performance and capacity provided by a "fast SPICE" tool, designers can simulate, at the transistor level, not only parts but also the entire chip. Although this approach provides a way to analyze the circuit functionality and timing in a fullchip context, it becomes very compute intensive due to the inherent difference in gate and transistor level simulation speeds. If the digital portion of the design has standard CMOS logic, with rail-to-rail swings, transistor-level simulation for this portion is overkill. Also, waiting until the end of the design cycle to perform a full chip simulation delays detection of flaws that may have crept in during the specification phase.

NanoSim Technology
High-Performance, High-Capacity Transistor-level Simulation
NanoSim is a high-performance transistor-level circuit simulation and analysis tool. It is a robust and easy to use solution, with simulation speeds orders of magnitude higher than SPICE, with the capacity for multimillion transistor designs, and SPICE-like accuracy for designs at 0.13 micron and below.

NanoSim’s high performance and capacity are achieved by using intelligent partitioning techniques along with a combination of event-based and time-based simulation. A typical SPICE engine treats the entire design as one monolithic block and evaluates all nodes at each time step. NanoSim on the other hand, uses a “divide and conquer” approach (Figure 1); the design is automatically partitioned into smaller stages based on the channel connectivity. Thus, any given stage or partition is evaluated only when an input controlling node is triggered, hence not all stages are evaluated at each time step. Independent simulation of these smaller stages also helps in DC and transient convergence.

Figure 1: Traditional SPICE versus NanoSim

NanoSim achieves a trade-off between accuracy and performance by using a range of device models, such as the piece-wise linear (PWL) model used for digital logic and ACC, accurate model, for analog bias, illustrated in Figure 2. NanoSim automatically detects various topologies in the design, such as analog bias circuits and digital cells, and then uses the appropriate device models for these topologies. This ensures that a wide spectrum of designs, ranging from highly analog Phase Lock Loops, digital custom logic and mixed-signal circuits such as Digital Signal Processors, can be accurately simulated. Close correlation to silicon is maintained by accurate modeling of deep sub micron (DSM) effects, such as voltage dependent Miller terms, crosstalk analysis and ground bounce effects.

Figure 2: Example of device models used by NanoSim

NanoSim comes with a comprehensive set of timing and power diagnostic functions that facilitate design debugging and can help avoid silicon re-spins by identifying design flaws in the early phases of the design. NanoSim supports all major SPICE netlist and model formats making it an easy fit into any methodology. It comes with an intuitive setup and simulation environment GUI.

Behavioral Modeling Using Verilog-A
NanoSim has built-in support for the Verilog-A language, an HDL for analog systems derived from the IEEE 1364 Verilog specification. Verilog-A allows users to define analog behavioral descriptions that encapsulate high-level behavioral and structural descriptions of systems and components. Verilog-A modules are used to describe the behavior of circuit components mathematically in terms of its ports and parameters applied to an instance of the module.

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Figure 3: Example of a Linear Phase Locked Loop (PLL) system with its Voltage Controlled Oscillator (VCO) modeled in Verilog-A

The Verilog-A language allows descriptions of conservative systems and also can be used to describe higher-level or signal-flow systems. NanoSim further adds to this capability with the Analog Digital Functional Modeling Interface (ADFMI) extensions to Verilog-A, to enable development of event-driven discrete models. ADFMI is a Synopsys proprietary, C-language modeling extension used primarily for adding event-driven and functional models to NanoSim.

Compared to simulating Verilog-A modules with other full SPICE-based simulators, NanoSim provides a key performance advantage since it uses the same NanoSim high-performance “fast SPICE” engine. NanoSim’s support for Verilog-A provides designers with a way to verify the entire system at the specification level to allow better architecture and IP selection, independent of the underlying silicon technology.

NanoSim Integration With VCS
VCS™, Synopsys Verilog simulator, provides the high performance and capacity required to verify today’s multi-million gate designs and uniquely raises productivity with “Smart Verification” technology. VCS supports mixed-language simulation, massive simulation server farm deployment, powerful testbench creation, coverage feedback, advanced debugging techniques, and comprehensive ASIC vendor sign-off.

NanoSim is tightly integrated with VCS enabling the powerful combination of gate-level performance with transistor-level accuracy. This integration is based on a direct kernel-to-kernel interface between the two tools, and is consequently optimized for performance.

NanoSim integration with VCS uses a unique mechanism for translation of logic-to-voltage and voltage-tologic at the digital and analog boundary. A resistance map table is used to equate the digital signal strength to a driving resistance for digital-to-analog (D2A) translation and for analog-to-digital (A2D) translation, the MOSFET on resistance to equivalent digital signal strength. The user can create a custom resistance map table or can use the default resistance map file.

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Figure 4: A2D/D2A translation mechanism used by NanoSim-VCS interface, along with the equivalent electrical model

The NanoSim-VCS combination automatically handles level shifting between blocks, by allowing for different voltage supplies for different blocks. When computing the signal voltage at the digital and analog boundary, the individual voltage supply of the connected transistor block is used. If needed, the reference voltage supplies can be overridden to reflect the supply of the digital block. This flexibility helps in analyzing correct signal levels between analog and digital blocks and avoids floating gate and forward biased diode errors in the design.

The usage model for NanoSim integration with VCS is easy, allowing direct instantiation of SPICE blocks within Verilog and vice versa, requiring no netlist modifications, running the simulation with a simple switch and generating waveform output for both digital and analog signals in a single file.

Advanced Mixed-Signal Design Verification Techniques
With its high-performance transistor simulation engine, tight VCS integration, and built-in support for Verilog-A, NanoSim provides a highly flexible solution for mixed-signal verification that fits into any design flow. This solution can be used to simulate any combination of behavioral, RTL or gate-level modules described in Verilog or VHDL, and custom analog or digital blocks described in Verilog-A or SPICE.

Top-Down Mixed-Signal Design Verification

The traditional digital ASIC flow is top-down with respect to levels of abstraction. The design starts at the highest level of abstraction, i.e. behavioral or RTL level, moves to gate-level using synthesis techniques and then to the physical domain in the GDSII chip-layout format. As the design cycle progresses, it verified at all levels of abstraction, using HDL simulators.

When designing mixed-signal SoCs, this flow changes, because there is the need to bring in custom digital and analog blocks and to verify the full-chip for functional and timing compliance. The NanoSim-VCS combination facilitates this flow by allowing the designer to stay in their familiar VCS-based environment and being able to easily import analog blocks without any netlist or testbench modifications. Using Verilog-A behavioral models for the analog portion, in conjunction with behavioral Verilog/VHDL digital models, accelerates the full-chip functional verification in the early stages of the design. As the design cycle progresses, and the design of the analog blocks is completed, the Verilog-A behavioral models can be swapped out with the full transistor-level netlist.

Figure 5 illustrate two different simulation views for the same design, the left one with the Verilog testbench and models for digital and Verilog-A models for the analog circuits, and right one with the transistor-level SPICE netlist.

The ability to simulate the HDL and SPICE blocks together in the full-chip context not only helps ensure that the digital and analog interfaces are working, but can also provide up to 100x speed-up in simulation through-put, compared to a full-chip transistor-level simulation. Another advantage of this Verilog-top based, mixed-signal simulation flow, is the ability to continue using self-checking regression test benches, typical in the digital simulation environment, to enable quick iteration and verification of changes to the circuits.

Bottom-Up Mixed-Signal Design Verification
The traditional analog and mixed-signal design flow is bottom-up. It starts from block level design using schematic capture, and as the individual components are completed, the system is brought together. The design is captured in SPICE format, including the top-level netlist. NanoSim allows the designers to stay in a familiar SPICE-like environment and easily include blocks of digital logic in Verilog/VHDL in a full-chip context. An example application of this would be the ability to import a Verilog model for an embedded memory into a mixed-signal simulation as shown below in Figure 6.

Figure 6: Example of mixed-signal design with a SPICE-top hierarchy, instantiating a Verilog-D and Verilog-A block

NanoSim allows designers to use Verilog-A behavioral models, to specify not only analog charge conservative systems, but also more digital event-driven models using the ADFMI extensions. This easy mechanism for specification of mixed-level systems gives designers the ability to explore different architectures independent of the underlying silicon technology.

Some Customer Experiences
Here are examples from some leading semiconductor vendors, of successful application of the Synopsys’ multi-level mixed-signal verification solution based on NanoSim, its VCS integration and Verilog-A technology.

• A leading testing and interconnection solution provider used NanoSim integration with VCS for verifying its latest mixed-signal SoC device. This methodology allowed integration issues to be discovered earlier in the design process and helped avoid costly silicon re-spins. Some examples of the design issues identified a severe defect in the initialization of a section of the analog digital interface and a mismatch between the Verilog behavioral model of an analog block and it’s SPICE netlist.
• A leading semiconductor vendor of communications solutions deployed NanoSim with Verilog-A and VCS to verify that the software being developed for controlling their SoC design was working, by using a high-level abstraction of the mixed-signal design in Verilog and Verilog-A models, months before the actual silicon was available for this level of testing.
• A leading wireless and embedded solutions provider has adopted NanoSim integration with VCS in their SoC verification flow for running a wide range of simulations, block, full-chip and even inter-chip. A number of mixed-signal design flaws were identified, such as a reversed driver signal from digital to analog block, leakage paths and floating gates leading to wasted battery power, and an inversed correction loop in digital control logic block. By catching these bugs early, software changes were made to account for known problems in silicon. The last chip-set silicon came back 99% functional.

Conclusion
The convergence of consumer electronics and personal computing continues to drive the need for more powerful, complex and highly integrated IC designs. At the same time, the demand to lower cost and power consumption in ICs — plus the ever-shrinking market window — results in more than 50% of today’s IC designs using SoC technology. Needless to say, designing such complex chips is a daunting task.

Equally challenging is the task of ensuring that the chips meet functional, timing and power specifications and work right the first time. According to an independent market study, at 0.13 micron, up to 45 percent of all designs will require at least one additional full mask-set iteration, costing close to $1 million per set. If you factor in the potential loss due to missing the market window, the cost becomes enormous.

NanoSim, with its high-performance engine for transistor-level simulation, tight integration with VCS and support for Verilog-A, provides a comprehensive solution for verification of these complex mixed-signal SoC designs. It provides the capacity and performance required for full-chip verification of designs with large digital and large analog components. NanoSim integration with VCS bridges the gap between verification methodologies, providing the flexibility to combine HDL, SPICE and Verilog-A behavioral models in any hierarchical combination. Identification of many costly bugs early in the cycle reduces time to market and lowers design costs by eliminating multiple design passes.