The Challenge
In today’s complex system-on-chip (SoC) designs, static and dynamic voltage-drop and electromigration (EM) effects are increasing. At 90 nanometers (nm) and below, these effects are having a profound impact on timing, contributing 10 to 15 percent delay sensitivity in today’s designs. These effects stem from:

• The use of smaller process geometries and lower supply voltages, which reduce the noise margins and make often-used over-design techniques implausible.
• Increasing device integration with higher operating frequencies, which increase the chance of voltage-drop on inductive components of both package and on-chip (Ldi/dt) power network.

Power network analysis solutions that offer static analysis, alone, are inadequate to address these problems. Such solutions rely on over-design of the power network, and result in inefficiently routed designs with large die sizes. Likewise, existing gate-level dynamic analysis solutions fail to accurately model memories when performing full-chip dynamic analysis. Moreover, these solutions are not integrated within the implementation platform, leading to a cumbersome and non-convergent flow.

The Solution
PrimeRail is a full-chip dynamic voltage-drop and electromigration (EM) analysis solution that enables power network sign-off in Synopsys’ Galaxy™ Design Platform. PrimeRail extends Synopsys’ industry-leading sign-off solution to power networks.

Building on Synopsys’ silicon-accurate Star-RCXT™, HSPICE®, NanoSim® and PrimeTime® sign-off technologies, PrimeRail delivers accurate modeling of memories and analog circuits.

As a key component of Galaxy, PrimeRail delivers a predictable path to sign-off, including:

• Design planning with JupiterXT™. PrimeRail delivers vector-free dynamic analysis and memory models for voltage-drop prediction.
• Physical design with IC Compiler. PrimeRail delivers dynamic analysis with parasitics and HSPICE-accurate memory models for power network optimization during physical design.
• Power network sign-off with PrimeTime®/PrimeTime SI and Star-RCXT™. PrimeRail delivers post-layout static or dynamic analysis with on-chip decoupling capacitance and package parasitics. With PrimeRail, customers can now acheive comprehensive power network sign-off.

Key Features and Benefits

• Hybrid technology
  Innovative engine delivers gates and transistor-level static and dynamic voltage-drop and EM analysis within one to two percent of HSPICE. It provides full-chip performance/capacity for arbitrary RLC (resistance, inductance, capacitance) networks. Its high-speed and memoryefficient architecture enables analysis of 20M gates in 8 hours with minimized memory usage. It supports design formats in Milkyway, LEF/DEF, or GDSII.
• Accurate Dynamic Modeling of Memories and Analog
  PrimeRail’s unique simulation and modeling capability delivers accurate memory and analog models with HSPICE correlation. Memories in GDSII format are simulated using NanoSim while Star-RCXT is used for power-ground and signal parasitic extraction to provide highest accuracy.
• Power Network Sign-off
  PrimeRail’s tight integration with PrimeTime enables full-chip power network sign-off. PrimeRail produces dynamic voltage-drop waveforms for each cell in the design, enabling PrimeTime to predict delay and timing more accurately for concurrent STA, SI and power network sign-off.

Additional features round out complete support for power network sign-off

• Automatic generation of current waveform power libraries using HSPICE
• Hierarchical and flat analysis
• Vector-free, vector-based dynamic analysis
• Embedded power network extraction
• Decoupling capacitance and package RLC analysis
• “What-if” analysis
• Voltage-drop and EM maps
• TCL support
• Analysis of advanced low power design techniques: Multi-voltage, power gating

Related Products

• HSPICE
• IC Compiler
• Milkyway
• NanoSim
• PrimeTime
• Power Compiler
• Star-RCXT

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