PrimeRail

Overview
PrimeRail is a full-chip power network analysis solution for low power and high performance designs at 90-nanometer (nm) and below. PrimeRail offers gate-level and transistor-level static and dynamic voltage-drop and electromigration (EM) analysis during implementation and sign-off. PrimeRail is the power network extension to Synopsys' industry-leading sign-off solution in the Galaxy™ Design Platform. Built on gold standards Star-RCXT™ extraction and PrimeTime® sign-off technologies, PrimeRail delivers the highest accuracy, performance and capacity advantage. PrimeRail's integration with the Galaxy Design Platform allows designers to achieve fast design convergence and a predictable path to sign-off.

Figure 1: Synopsys' sign-off solution in Galaxy Design Platform

Key Features and Benefits

• Full-chip static and dynamic power network sign-off for gates and transistors
• Multi-mode analysis of advanced low power designs using multiple voltage islands and multi-threshold-CMOS (MT-CMOS) / power-gating cells
• Fast and accurate dynamic modeling for memories, analog, custom IP
• Leading performance and capacity for multi-million gate system-on-chip (SoC) designs
• Proven accuracy – within 5% of HSPICE®
• Galaxy Design Platform integration for productive and predictable design
• Flexible analysis throughout the flow – voltage-drop prediction during design planning, pre-layout analysis and final sign-off
• Liberty™ Composite Current Source (CCS) Power library support
• Built-in library characterization utility for dynamic current waveforms
• Embedded full-chip parasitic extraction
• System and package RLC support
• Vector-free and vector-based dynamic analysis
• Integration with PrimeTime tool for concurrent static timing analysis (STA), signal integrity (SI) and voltage-drop sign-off
• ECO fix for voltage-drop using decoupling capacitances
• "What-if" analysis for debug and optimization, esp. decoupling capacitance Vs voltage-drop Vs leakage trade-offs
• Detailed reporting and graphical user interface for pin-pointing hot spots
• TSMC Reference Flow 7.0 certified

Figure 2: PrimeRail – full-chip transistor-level and gate-level voltage-drop and EM sign-off solution

Full-chip Power Network Analysis Solution
In today's complex SoC designs, static and dynamic voltagedrop and EM effects are increasing. At 90-nm and below, these effects are having a profound impact on timing – contributing 10 to 15 percent delay sensitivity, and overall on design viability. These effects stem from:

• The use of smaller process geometries and lower supply voltages, which reduce the noise margins and make often-used over-design techniques implausible.
• Increasing device integration with higher operating frequencies, which increase the chance of voltage-drop on inductive components of both package and on-chip (Ldi/dt) power network.
• Increasing use of low power design techniques, such as multiple voltages and power management switches, which reduce power consumption but exacerbate the dynamic voltage-drop and EM problems.

Power network analysis solutions that offer static analysis, alone, are inadequate to address these problems. Such solutions rely on overdesign of the power network, and result in inefficiently routed designs with large die sizes. Likewise, existing gate-level dynamic analysis solutions fail to accurately model memories when performing full-chip dynamic analysis. Moreover, these solutions are not integrated within the implementation platform, leading to a cumbersome and non-convergent flow. PrimeRail is industry's first solution to offer a single solution for transistor-level and gate-level analysis that is integrated with the industry leading Synopsys Galaxy Design Platform.

Figure 3: PrimeRail offers static and dynamic analysis throughout the implementation flow

Transistor-level Analysis
PrimeRail provides dynamic voltage-drop and power-ground and signal EM analysis solution for memories, analog-mixed signal (AMS) and digital custom designs. PrimeRail is integrated with industry leading Star-RCXT parasitic extraction solution and fastspice circuit simulators HSIMplus and NanoSim® for transistor-level analysis. It provides leading performance and capacity, analyzing 25 million transistor design in less than 10 hours. PrimeRail delivers high accuracy within 2% of HSPICE for RC and inductive noise analysis.

Gate-level Analysis
PrimeRail offers full-chip hierarchical analysis for ASIC and SoC low power and high performance designs. It's high-speed and memory efficient architecture enables analysis of 20M gates in 8 hours with minimized memory usage. It supports design formats in Milkyway™, LEF/DEF, or GDSII.

PrimeRail fully supports Liberty CCS Power libraries required for dynamic rail analysis. Alternatively, it provides a built-in library characterization capability for power-ground current waveform and cell intrinsic parasitic modeling to augment information available in industry-standard Liberty non-linear delay model (NLDM) libraries. PrimeRail uses golden HSPICE simulator and distributed processing for accurate, high speed characterization.

Embedded silicon-accurate and proven power-ground parasitic extraction technology in PrimeRail supports arbitrary resistance and capacitance networks and is correlated with industryleading Synopsys' Star-RCXT parasitic extraction solution.

Figure 4: PrimeRail decoupling capacitors “what if” analysis and ECO flow enables easy diagnosis and fix

PrimeRail also supports detailed lumped or distributed RLC models for package in SPICE format for comprehensive system-level dynamic analysis.

PrimeRail supports vector-free and switching-activity interchange format (SAIF), RTL and gate-level VCD vector-based power analysis for instance based current waveform generation required for rail analysis. It leverages industry-leading timing and power analysis technology from PrimeTime and PrimeTime PX for proven sign-off accuracy.

PrimeRail is integrated with PrimeTime enabling full-chip power network sign-off. PrimeRail produces average, RMS or peak voltage-drop values for a simulation period or timing window, enabling PrimeTime to predict delay and timing more accurately for concurrent STA, SI and power network sign-off.

Graphical user interface based "what if" analysis capability in PrimeRail enables ease-of-use in debugging, pin-pointing and exploring trade-offs to optimize the design for voltage-drop, performance and desired power consumption. Designers can easily investigate the impact of on-chip decoupling capacitors (decaps) and add or remove decaps to meet the design requirements. The automated decap ECO flow delivers enhanced productivity in analysis and design closure.

Accurate Dynamic Modeling of Memories
PrimeRail's unique and flexible Dynamic White-box Modeling (DWM) capability delivers accurate models for memories, custom IP and analog blocks with HSPICE correlation.

Memories in GDSII format are simulated using NanoSim or HSIMplus while Star-RCXT is used for power-ground and signal parasitic extraction to provide highest accuracy models. In addition, simulation-free DWM Lite modeling capability allows fast generation (>10X faster) of macro-models for use earlier in the flow without adversely compromising accuracy.

Figure 5: PrimeRail optimizes MT-CMOS low power designs to mitigate rush current related design failures

Low Power MTCMOS Design Analysis
Leakage power has become a daunting challenge in sub 90-nm designs, especially for consumer and wireless applications. Advanced low power design techniques, such as multiple supply voltages, dynamic voltage scaling and MTCMOS power-gating switches are frequently used to reduce leakage power consumption. MT-CMOS switches, for instance, shut-off power supplies to parts of a design to significantly reduce leakage power in inactive or sleep mode of operation. However, increasing use of these switches and power on/off operation worsens the on-chip current gradients and exacerbate the power network integrity problems due to rush current.

PrimeRail performs full-chip dynamic voltage-drop and EM analysis of low power multi-voltage designs using MTCMOS power gating switches. It offers accurate modeling of coarseor fine-grained switches, and analysis of rush current and wake-up time during power-up to active mode. PrimeRail's multi-mode analysis enables designers to optimize the on-off operating sequence of the MTCMOS switches to mitigate the risks of design failure. In addition, the “what if” analysis capability allows easy design trade-offs to meet both leakage and voltage-drop requirements throughout the implementation.

Galaxy Design Platform Integration
As a key component of the Galaxy Design Platform, PrimeRail is integrated with Synopsys' implementation environment via Milkyway database, delivering a predictable path to sign-off.

• Design planning with JupiterXT™ tool: PrimeRail delivers vector-free dynamic analysis and memory models for voltage-drop prediction.
• Physical design with IC Compiler: PrimeRail delivers dynamic analysis with parasitics and HSPICE-accurate memory models for power network optimization during physical design.
• Power network sign-off with PrimeTime/PrimeTime SI and Star-RCXT: PrimeRail delivers post-layout static or dynamic analysis with on-chip decoupling capacitance and package parasitics. With PrimeRail, customers can now achieve comprehensive power network sign-off.

Specifications

System Requirements

• DRAM: 512MB, recommend 1GB
• Swap Space: 512MB, recommend 2GB
• Installation disk space: 250MB baseline plus 250MB per platform
• Design disk space depends on the circuit size, recommended minimum 500MB/li>