VCS Archives

Press Releases

• Renesas Adopts Synopsys' VCS Solution and VMM Methodology
• Wolfson Selects Synopsys Galaxy and Discovery Platforms and DesignWare IP
• Synopsys and Freescale Sign Verification Agreement
• Enterasys Adopts Synopsys' VCS Native Testbench
• Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers
• Industry Momentum Builds for the ARM-Synopsys VMM for SystemVerilog
• S3 Adopts Synopsys' VCS Verification Solution and the Verification Methodology Manual for Systemverilog
• SEQUANS Standardizes on Synopsys VCS, System Studio and Formality Solutions
• Synopsys Delivers First Complete SystemVerilog Design and Verification Flow
• AMCC Speeds Verification Using Synopsys' VCS with SystemVerilog
• Exar Triples Verification Productivity Using VCS with SystemVerilog
• Aarohi Deploys Synopsys' VCS Native Testbench
• Sun Microsystems and Synopsys Collaborate to Certify VCS Verification Solution
• STMicroelectronics Cuts Verification Time In Half with VCS
• VCS Solution Adds Assertion IP Library and Native Testbench Support for SystemVerilog
• Synopsys Introduces VCS Verification Library to Speed Verification by Up to 5X
• Huawei Adopts Synopsys VCS Native Testbench to Accelerate Verification of Networking and Communications ASICS
• Atmel Adopts Synopsys' VCS Native Testbench
• Silicon Logic Engineering Uses VCS and Vera Solutions
• Cedar Point Utilizes Synopsys' VCS Native Testbench
• Synopsys Introduces VCS Verification Library to Speed Verification by Up to 5X
• Top Layer Uses Synopsys Testbench Automation Tool
• Faraday Verifies Complex CPU Cores with Synopsys' VCS and Vera Verification Solutions
• CréVinn Adopts Synopsys' VCS Native Testbench to Accelerate ASIC Development
• Synopsys, Inc. Announces Technical Seminar Series Featuring Verification, Implementation, and Design-For-Manufacturing Solutions
• Synopsys Introduces Migration Service from Verisity Specman Elite to Synopsys VCS Verification Solution
• Mentor Graphics and Synopsys Offer SystemVerilog Seminars for Users of the Verisity e Language

Articles

• Simplify the Setup of Constrained - Random-Test Environments
• SystemVerilog Reference Verification Methodology: VMM Adoption
• Synopsys & SystemVerilog Verification Methodology Manual (VMM)
• More On Power, ESL, And DFM
• SystemVerilog reference verification methodology: ESL
• SystemVerilog: The Complete Solution
• SystemVerilog reference verification methodology: RTL
• SystemVerilog reference verification methodology: Introduction
• Transaction-Level Modeling: SystemC and/or SystemVerilog
• EE Times: Synopsys Offers Verisity Migration
• Electronic News: Synopsys Woos Verisity Users with Migration Service
• EE Times: Synopsys Offers Verisity Migration Plan
• EE Times: Coverage is the Heart of Verification
• Electronic Design: Testbench Technology Shores Up Simulator's Verification Capabilities
• EEdesign: Synopsys adds testbench features to VCS
• EEdesign: Synopsys forum updates SystemVerilog support
• EEdesign: How to Choose a Verification Methodology
• EE Times: Mixed-Signal Verification Methodology Using Nanosim
• SystemVerilog assertions unify design and verification
• Design for verification methodology allows silicon success

White Papers

• Successful Mixed-Language Code Coverage with VCS
• How to Get Started with SystemVerilog Assertions
• Assertions in SystemVerilog, A Unified Language for More Efficient Verification