Overview
In the ongoing drive towards smaller, faster and cheaper chips, the worlds of design and manufacturing are colliding. Where once there were distinct lines separately the worlds between GDSII and mask making, the need for communication and collaboration is becoming a necessity. Designs can no longer be thrown over the wall for production.

Challenge
This emerging trend is the result of a new phenomenon called: Subwavelength gap. Once process geometries hit the 130 nm mark, a new phenomenon occurred in which the actual wavelength of light and the geometry nodes were of equal size. This presents a significant challenge in the subwavelength realm. The light distortions caused by subwavelength lithography are not considered by the traditional process rules that are used to drive IC design, photomask manufacturing, or photomask and wafer inspection.

The need for a holistic approach between design and manufacturing is required.

Solution
Synopsys offers the only complete RTL- to-Silicon solution through it’s Galaxy™ Design and Discovery™ Verification Platforms and DFM product offerings.

The combined use of Synopsys' platforms and DFM products allows customers to establish the critical links between design and manufacturing that are necessary to implement and ramp manufacturable, high yielding processes at the 90, 65 and 32 nm process nodes

Synopsys offers solutions in each of the critical, mask synthesis, mask data preparation, TCAD, lithography simulation, lithography verification, and manufacturing yield management steps in order to help ensure your design is manufacturable at 90 nm nodes and smaller.

Design for Manufacturing Product Family