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Overview
Discovery supports a range of mainstream languages for the design and verification of chips: SystemVerilog, SystemC, OpenVera and VHDL. Users choose languages based on their own specific needs, requirements and experience, and are able to execute a variety of different design and verification methodologies using the Discovery Verification Platform.
- Key Benefits
- Working with industry-standard languages removes risk from the design process
- An integrated language solution enables the efficient exchange of models and code
- Support for multiple abstraction levels promotes reuse at different stages of the design flow
Design Challenges
Today's system-on-a-chip designs require engineering teams with multiple skill sets covering embedded software, system architecture, RTL design and verification. Traditionally these teams have used a variety of 'C' modeling styles for architecture and application design and a variety of hardware description languages (HDLs) and hardware verification languages (HVLs) for RTL design and verification. This has led to complex design flows that prevented reuse, and conflicted with the time-to-market and development cost pressures for SoCs.
SystemC and SystemVerilog
SystemC is used for modeling algorithms at an untimed level and for modeling SoC architectures at the transaction level. Transaction-level modeling enables intellectual property and platform providers to offer high-level representations of a complete chip, sub-system, or individual IP block, which can be used to analyze architectural tradeoffs and for early application software verification. SystemC is a language well suited to create, simulate, and analyze transaction-level models of the design, and can be appreciated by design engineers with a C/C++ background.
SystemVerilog is used for hardware design and verification to describe concise, synthesizable RTL, and designing effective, thorough testbenches and assertions for native-simulation based verification, including formal property verification. SystemVerilog is ideal for capturing the hardware implementation and the verification environment, and may be preferred by some verification engineers for transaction-level models.
A complete verification solution for today’s complex chips therefore consists of a well-implemented integration of SystemC and SystemVerilog that enables the verification of mixed (transaction and hardware) models. This integration allows the powerful features of SystemVerilog for verification to be fully leveraged for transaction-level model verification while the same testbenches are used for hardware verification. By bringing SystemC and SystemVerilog together in a single modeling and verification environment, architectural exploration and tradeoffs can be made before the final hardware-software partition is settled. Software can be developed early in the project cycle and also verified to operate correctly in the context of the architecture as well as the hardware.
Solution
The Synopsys solution centers on the IEEE standardized languages SystemC and SystemVerilog while providing strong support for Verilog, VHDL, and OpenVera.
- Standards-Related Links
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