Mixed-Signal Design + Verification Archive

Press Release

• Synopsys Discovery AMS Delivers New Level of Performance and Accuracy for Integrated Analog and Mixed-Signal Verification
• Virage Logic Adopts Synopsys' HSPICE Simulator as Golden Simulator for 65-nm Library Sign-off
• Altera Deploys Synopsys' STAR-RCXT Extraction Tool and HSIM Simulator to Achieve Silicon-Accurate 65nm Designs
• Synopsys' HSPICE High-Voltage MOS Transistor Model Adopted by UMC
• Oki Standardizes on Synopsys' HSPICE High Voltage MOS Model
• Synopsys and X-FAB Team To Accelerate Analog Mixed-Signal IC Design
• Synopsys' HSPICE High-Voltage MOS Transistor Model Adopted by UMC

SNUG User Papers

• LG Electronics: Using NanoSim for Video Signal Digitizer Design
• Atmel: Full Chip Verification Using NanoSim
• LG Electronics: Using NanoSim for Video Signal Digitizer Design
• SUNPLUS: Using NanoSim for Mixed-Level Simulation
• Motorola: Verification of Large Mixed-Signal SoC Using NanoSim and VCS
• ST Microelectronics: NanoSim in Memory Characterization Flow
• xSUNPLUS: Using NanoSim for Mixed-Level Simulation
• Teradyne + ASIC North: Mixed-Signal Verification Using NanoSim and VCS
• VIA: NanoSim and VCS Application for SoC Design

Articles

• EE Times: Synopsys, Zuken tie simulation to boards
• Deploying the right tools for mixed signal verification
• Chip Design Magazine: Start at the Top to Reduce Re-Spins for Analog-Digital Chips
• EE Design: What's needed for mixed-signal verification

Webcast

• Predicting PLL Phase Noise & Jitter with HSPICE RF
• Robust SI Analysis of a DDR2 Interface with HSPICE
• Jan 23 Webcast
  Predicting PLL Phase Noise & Jitter with HSPICE RF
• HSIM^plus Beyond Fast SPICE Simulation
• Synopsys’ Comprehensive Full-Chip Verification Solution