Discovery Verification Platform - Archives

Press Release Archive

• Synopsys HSPICE Simulator Accelerates ARM's 45-Nanometer Physical IP Development
• Synopsys HSPICE Simulator and SISoft Deliver Signal Integrity Analysis Solution
• Agilent Technologies Announces HVMOS Package for Synopsys' HSPICE
• Synopsys Launches VMM Catalyst Program with More Than 50 Member Companies
• Synopsys and Zuken to Deliver Integrated, Robust PCB Design and Simulation Solution
• Synopsys and Synplicity Establish Alliance to Advance High-Performance ASIC Verification
• Leading Semiconductor Companies in China Adopt the VMM Verification Methodology
• Synopsys Discovery AMS Delivers New Level of Performance and Accuracy for Integrated Analog and Mixed-Signal Verification
• Synopsys Accelerates Low-power Designs with Comprehensive Implementation and Verification Solution
• Synopsys Extends VMM Methodology for Higher Functional Verification Productivity
• Renesas Adopts Synopsys' VCS Solution and VMM Methodology
• Wolfson Selects Synopsys Galaxy and Discovery Platforms and DesignWare IP
• Synopsys and Freescale Sign Verification Agreement
• Enterasys Adopts Synopsys' VCS Native Testbench for Accelerated Verification Productivity
• Synopsys Enhances Saber Simulator Integration with UGS Software Through Global UGS Partner Program
• Virage Logic Adopts Synopsys' HSPICE Simulator as Golden Simulator for 65-nm Library Sign-off
• Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers
• Industry Momentum Builds for the ARM-Synopsys VMM for SystemVerilog
• S3 Adopts Synopsys' VCS Verification Solution and the Verification Methodology Manual for SystemVerilog
• Synopsys Provides EDA Solution for SUN Microsystems' UltraSPARC T1 Processor
• Synopsys Delivers First Complete SystemVerilog Design and Verification Flow
• Synopsys Announces EDA Industry's First Verification IP Library for SystemVerilog with Methodology Support
• Leading Japanese Semiconductor Vendors Endorse ARM-Synopsys VMM for SystemVerilog
• Exar Triples Verification Productivity Using VCS with SystemVerilog
• Synopsys Introduces Pioneer NTB for SystemVerilog Testbench Automation
• Synopsys and X-FAB Team To Accelerate Analog Mixed-Signal IC Design
• Synopsys' HSPICE High-Voltage MOS Transistor Model Adopted by UMC
• Aarohi Deploys Synopsys' VCS Native Testbench
• Sun Microsystems and Synopsys Collaborate to Certify VCS Verification Solution
• STMicroelectronics Cuts Verification Time In Half with VCS
• VCS Solution Adds Assertion IP Library and Native Testbench Support for SystemVerilog
• Huawei Adopts Synopsys VCS Native Testbench to Accelerate Verification of Networking and Communications ASICS
• Atmel Adopts Synopsys' VCS Native Testbench
• Silicon Logic Engineering Uses VCS and Vera Solutions
• Cedar Point Utilizes Synopsys' VCS Native Testbench
• Synopsys Introduces VCS Verification Library to Speed Verification by Up to 5X
• Top Layer Uses Synopsys Testbench Automation Tool
• Faraday Verifies Complex CPU Cores with Synopsys' VCS and Vera Verification Solutions
• CréVinn Adopts Synopsys' VCS Native Testbench to Accelerate ASIC Development
• Synopsys, Inc. Announces Technical Seminar Series Featuring Verification, Implementation, and Design-For-Manufacturing Solutions
• Synopsys Introduces Migration Service from Verisity Specman Elite to Synopsys VCS Verification Solution
• Mentor Graphics and Synopsys Offer SystemVerilog Seminars for Users of the Verisity e Language

Articles

• SCDSource: 'Off by Design' architectures curb energy waste
• IC Design & Verification Journal: Migrating Complex Networking ASIC Verification Environment
• EDN: Synopsys tries to organize its efforts in EDA multiprocessing
• Electronic Design: Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli
• SCDsource: Synopsys pledges multicore support for EDA applications
• SCDsource: Formal property checking—what the vendors say
• EDA Tech Forum: How VHDL designers can exploit SystemVerilog
• EDN: VMM application packages: the next level of productivity
• SCDsource: Three verification improvements boost functional coverage
• SCD Source: Formal property checking -- what the users say
• SCDsource: Coverage metrics not enough, verification experts say
• Chip Design: Nightmares in Functional Verification
• EDN: IC verification key: ‘Do it step by step, don’t cut corners’
• Future Verification Appears Uncertain
• Detecting Leakage Problems in Low-Power Designs
• Power-Sensitive 65nm Designs Increase the Need for Transistor-Level Verification
• EE Times: Synopsy, Zuken tie simulation to boards
• Synopsys Extends SystemVerilog Verification
• Synopsys & SystemVerilog Verification Methodology Manual (VMM)
• SystemVerilog Reference Verification Methodology: VMM Adoption
• SystemVerilog reference verification methodology: ESL
• SystemVerilog: The Complete Solution
• EE Times: SystemVerilog reference verification methodology: RTL
• EE Times: SystemVerilog reference verification methodology: Introduction
• Transaction-Level Modeling: SystemC and/or SystemVerilog
• EE Times: System Verilog users speak out
• EE Design: Synopsys claims enhanced tool can speed verification by up to 5X
• EE Times:Coverage is the heart of verification
• EE Times: Synopsys Offers Verisity Migration
• Electronic News: Synopsys Woos Verisity Users with Migration Service
• EE Times: Coverage is the Heart of Verification
• Compiler: Verification=IP=Verification=IP=...
• Electronic Design: Testbench Technology Shores Up Simulator's Verification Capabilities
• EEdesign:Synopsys adds testbench features to VCS
• EEdesign: Design-for-verification methodology allows silicon success (April 2003)
• EE Times: Synopsys upgrades VCS and Vera (Feb 2003)

Webcasts

• Feb 23 Webcast
  Robust SI Analysis of a DDR2 Interface with HSPICE
• Jan 23 Webcast
  Predicting PLL Phase Noise & Jitter with HSPICE RF
• Nov.7 Archived Webcast
  HSIM^plus – Beyond FAST Spice Simulation – Listen Now!
• Faster Verification Performance with VCS Native Testbench and RVM
• Static Verification with LEDA in Discovery Verification Platform
• Introduction to Assertion-Based Verification
• Introduction to SystemVerilog