Design for Low Power Archives

Press Releases

• Synopsys Introduces the Eclypse Low Power Solution
• Synopsys IC Compiler Successfully Employed by Matsushita for First 45-nm SoC Design Tapeout
• Synopsys Advances Low Power Management for Manufacturing Test
• eRide Converts to Synopsys Design Compiler Ultra for Next-Generation GPS Chips
• Synopsys and ARM Optimize Reference Methodology for Aggressive Power Management
• Unified Power Format, Open Analog Standards and Liberty Library Enhancements to be Featured at 19th EDA Interoperability Forum
• Synopsys Design Compiler 2007 Boosts Designer Productivity and IC Performance
• Synopsys Accelerates Low-power Designs with Comprehensive Implementation and Verification Solution
• Synopsys and UMC Enhance 90-nm Reference Flow with Advanced Low Power and Design for Test
• Synopsys Extends Liberty Modeling Standard to EnableVariation-Aware Design
• Galaxy Platform Reduces Power Consumption of Industry-Leading Multi-Voltage Designs
• Synopsys Continues IC Compiler Momentum with 2006.06 Release
• TSMC Names Synopsys to Distribute its Production-Ready 65-nm Nexsys Libraries
• Hisilicon Technologies Adopts Synopsys Galaxy Design Platform for Low-Power Design
• Synopsys, IBM, Chartered and ARM Collaborate to Extend Low-Power 90-nm Reference Flow
• IC Compiler Enables STMicroelectronics to Speed the Tapeout of Ultra-Low-Power Nomadik Multimedia Processor

Articles

• EE Times: Synopsys, ARM define low-power methodology
• EE Times: Low-power IC design techniques may perturb the entire flow
• EE Times: DASC approves low power format PAR
• EDA DesignLine: Test Methods Identify Small Delay Defects
• Test and Measurement World: ITC: Synopsys addresses yield, memory test, and small delay defects
• EE Times Asia: Flexible Analysis is Key to Power Integrity
• EE Times Asia: Achieve Low-Power Design Success at 65nm
• EE Times: Power integrity analysis for billion-transistor full-custom designs
• EE Times: Synopsys donates technology to Accellera low-power effort
• EE Times: Accellera Rolls Power Plan
• Test & Measurement: Limits of Test Time Reduction
• EE Times: How Much Test Compression is Enough?
• EE Times: Critical Area Optimizations Improve IC Yields