Galaxy Test Automation - PR Archive

Press Release Archive

• Synopsys Improves the Quality of Manufacturing Tests with Timing-Aware Pattern Generation
• Global Unichip Adopts Synopsys Test Solution to Achieve Higher SoC Test Quality
• Synopsys Lowers the Cost of Semiconductor Testing at Tessolve
• Cost-Effective, Ultra-High-Quality Test Results Using Synopsys DFT MAX Achieved at SHARP
• Open-Silicon Adopts Synopsys DFT MAX to Lower the Manufacturing Cost of ASICs
• Synopsys Design Compiler 2007 Boosts Designer Productivity and IC Performance
• Synopsys TetraMAX Diagnostics for Rapid Yield Learning Adopted by UMC
• Synopsys DFT MAX Cuts Test Costs 90 Percent in Actions Semiconductor Designs
• Mplicity Standardizes on Synopsys Formality Solution for Verification of Multi-Core Design Flow
• OKI Adopts DFT MAX to Improve Test Quality
• SANYO Improves Test Quality with the Adoption of DFT MAX
• Synopsys TetraMax ATPG Diagnostics Now Linked with Synopsys Odyssey Yield Management System
• Synopsys and Virage Logic Collaborate on Test Reference Design Flow to Deliver Embedded Memory Test
• Semiconductor Firms Collaborate with Synopsys to Validate New ATPG Technology
• Synopsys Triples Automatic Test Pattern Generation Performance for TetraMAX Test Tool
• Synopsys DFT MAX Cuts Test Costs on Nanometer Designs
• Synopsys' DFT MAX Cuts Test Time and Cost on CSR Bluetooth Designs
• Synopsys' DFT MAX Reduces Test Costs on NVIDIA Graphics Processing Units

Articles Archive

• Design automation reshapes the foundry-client dynamic
• Electronic Design: The Benefits—And Hazards—Of Scan Compression
• EDA DesignLine: Measuring Scan Compression Performance
• EDACafe: Dr. Tom Williams – A Lifetime of Achievement
• EE Times Asia: Measure true ATPG performance improvements
• Test & Measurement: Optimizing compression in scan-based ATPG DFT implementations
• Test and Measurement World: ITC: Synopsys addresses yield, memory test, and small delay defects
• EDA Design Line: Test methods identify small delay defects
• EE Times Asia: Flexible Analysis is Key to Power Integrity
• EE Times Asia: Achieve Low-Power Design Success at 65nm
• EE Times: Power integrity analysis for billion-transistor full-custom designs
• EE Times: Synopsys donates technology to Accellera low-power effort
• EE Times: Accellera Rolls Power Plan
• EDA DesignLine: Power Integrity Analysis for Billion Transistor Full-Custom Designs
• Test & Measurement: Limits of Test Time Reduction
• EE Times: How Much Test Compression is Enough?
• EE Times: Critical Area Optimizations Improve IC Yields
• CTL: The New Language of DFT
• EE Times: EDA, test vendors ponder interoperability at DATE
• EE Times: Shifting from functional to structured techniques improves test quality
• EEdesign.com: Synopsys DFT tool gets core add on
• Evaluation Engineering: Where is DFT heading?