Key Benefits

• Production proven down to 65nm
• Optimal trade-offs between speed, area, power, test and yield.
• Industry standard sign-off timing and extraction
• Unmatched 3rd party support for technology libraries, services and IP.
• Provides fastest path to the best results

Design Challenges
Physical effects of semiconductors are becoming more and more interrelated. Each design decision can create unintended consequences. In addition to the old problems generated by wire capacitance, engineers can no longer manually balance the myriad effects such as leakage current, inductive noise or IR drop. Manufacturing processes and environmental variation can render your functional chip useless or economically unviable. Market forces are creating demands of higher volumes at lower and lower price points. Investors are losing their appetite for risk and paying a premium for predictable success. Designers must walk a tightrope of price and performance to reach their time-to-market goals.

Solution
Exponential advances of Moore’s Law have facilitated creative solutions to the very problems they have created. Advances in computing power coupled to innovative algorithms enable the Galaxy Design Platform to perform two essential functions:

1. Accurately model physical effects to guarantee timing
2. Concurrently evaluate trade-offs between design goals

Accurate modeling of physical effects such as noise and power enable the advanced algorithms of the Galaxy platform to push the envelope of achievable performance and minimize the drain of pessimistic margins. This extra performance is like money in the bank. The concurrent optimization engines spend this savings to minimize power consumption, reduce area, lower test costs or increase yield. All of this increases productivity by saving time and iterations spent on fixing unintended consequences.

The Galaxy Platform lets designers do what they do best – design!

Synthesis
RTL synthesis is no longer just about timing and area. The new measure of performance now includes low power, test and correlation with physical design, including prediction and alleviation of wire-routing congestion. Synopsys’ Design Compiler® family delivers this performance, making it the industry standard for logic synthesis. It offers broad language support for VHDL, Verilog, and SystemVerilog. In fact, more than 90 percent of ASIC designers trust Synopsys’ synthesis solution to deliver the optimum quality at the lowest risk. Key differentiators for the Design Compiler family are:

• Topographical-based synthesis delivers tight correlation between synthesis and physical design for timing, area, power, test and congestion, eliminating iterations previously needed to close on design goals. It cuts design time further through alleviation of routing congestion prior to physical implementation.
• Adaptive Scan test synthesis within the DFT MAX tool minimizes the cost of digital test by reducing test time and test data volume by 10-50Xwith push-button simplicity for the RTL designer
• Low-power automation offers design techniques for multi-Vth, multi-voltage, MTCMOS, low-power clock gating, and more
• Exhaustive formal verification of designs consisting of complex datapaths, retiming, and low- power circuits is completed in a fraction of the time vs. traditional dynamic techniques

Physical Design
Advances in silicon technology have made design-for-yield (DFY) a key requirement for designs at 90-nm and below. Synopsys’ IC Compiler tool is a next-generation place-and-route system that provides all the functionality necessary for high-quality physical design including floorplanning, physical synthesis, placement, routing, timing, signal integrity (SI) optimization, power reduction, design-for-test (DFT), and yield optimization. Key differentiators for the IC Compiler solution are:

• Extended Physical Synthesis (XPS) expands physical synthesis to full place-and-route to deliver better overall timing, area, power, SI, yield, and time-to-results
• Sign-off driven design closure integrates the Galaxy Platform’s sign-off tools with physical implementation to reduce design iterations
• Design for Yield enables concurrent optimization for yield, timing, area, power, routability, and signal integrity

Sign-Off
The Galaxy Design Platform delivers the industry’s most comprehensive sign-off solution. This solution encompasses support for timing analysis, signal integrity, power integrity, parasitic extraction, physical verification and automatic test pattern generation (ATPG). The PrimeTime® static timing analysis tool and the Star-RCXT™ parasitic extraction tool are the industry gold-standards as validated by the leading semiconductor companies and foundries. Synopsys’ sign-off solution helps ensure first-pass silicon success with greater predictability and higher productivity. Key differentiators for sign-off are:

• Comprehensive design analysis within the PrimeTime environment: timing, crosstalk delay, noise, power and voltage-drop delay analysis
• The Galaxy design platform fully supports the Composite Current Source (CCS) modeling technology. The unified CCS model for timing, noise and power, extends the analysis and optimization capabilities within the Galaxy Design Platform to concurrently address nanometer effects and thereby reduce design margins and minimizing iterations.
• The Star-RCXT tool supports gate-level, custom digital, memories, and analog/mixed-signal designs flows
• The TetraMax® ATPG leverages PrimeTime technology to deliver the highest defect detection with lowest test pattern count

For more information about this product, please contact your local Synopsys representative or call 1-800-388-9125.