Synopsys & Gennum Gennum Adopts VCS™ MX to Optimize Their Complex Verification Methodology

"Not only did Synopsys give us the path to meet our design schedule challenges, they also gave us a way to enhance our verification methodology and further increase our product quality."

Dave Simmons, Gennum Corporation, Director of Video Product Development

In the world of high-performance video components, on-time delivery and quality of products are paramount. Nobody knows this more than Gennum. Gennum Corporation is a Canadian high technology company that designs, manufactures and markets silicon integrated circuits (ICs), modules and thin-film hybrid microcircuit components. Among other businesses, Gennum is the leading provider of high-performance components to video equipment and systems manufacturers for broadcast television studios and production and post-production houses for video and film content creation and display.

Solutions

• VCS MX Mixed-HDL Simulator
• Scirocco™ VHDL Simulator

Features

• Next-generation region-based video correction system
• Multi-million gate design with over 20K lines of RTL code
• 200 MHz clock

Benefits

• Verification run-times moved from hours to minutes
• Synopsys simulators plugged into their current verification flow
• Strong roadmap provides access to coverage metrics and assertion-based verification

"We were growing very concerned with our current and future schedule deadlines. We didn’t see a way of meeting them without improving significant pieces of our verification flow. With VCS MX and Scirocco, we were able to quickly realize significant gains in simulation performance and throughput. Overall speed increases from our current simulation environment were up to 9.5x faster. Most importantly, we were able to do this with minimal impact on our existing verification flow."

Dave Simmons, Gennum Corporation, Director of Video Product Development

Recently, Gennum investigated ways to improve their verification methodologies. First and foremost, they sought to streamline and improve the quality of their verification environment. One of the goals was to reduce time and manpower requirements for verification of Image Processing ASICs, while causing a minimal impact on the remainder of their current verification environment. Ease of use was also a requirement for any and all changes to ensure high productivity from the engineering team.

For Gennum, simulation runs were taking many hours and in some cases, many days. Yet, simulator performance wasn’t the only problem. Gennum also needed an environment that easily integrated into their current verification flow, thus allowing for faster time-to-market.

The first results, using Synopsys’ VCS MX simulation platform were obtained within a matter of hours matching the results of their existing simulator. Next, the simulation profiler was used to identify RTL bottlenecks in the design; minor coding style changes were recommended and implemented allowing the design to exploit the full performance optimizations of Scirocco. Finally, VCS MX was brought in to perform the final Verilog gate-level simulation with their VHDL testbench.

Not only did the simulation performance improve, so did the capacity. The same designs were now simulating in one third less memory than their previous simulator. This would allow them to simulate their next designs on the same workstations used today.

Growing productivity and quality requirements were also investigated. With the advent of many new verification technologies, Gennum wanted to ensure that they could grow into these new methodologies with minimal risk to their existing design flow.

"Synopsys’ Smart Verification technology gives customers just what they want; the ability to easily adopt integrated testbench, advanced coverage and assertion-based verification into their design flow at a pace that is best suited our customers without additional tools required," said Robert Beanland, Director of Product Marketing for HDL Simulation at Synopsys.