DFT MAX Adaptive Scan Compression Synthesis

Overview
DFT MAX is a comprehensive scan compression synthesis and compression solution that address design and test challenges occurring in 130-nm, 90-nm and smaller process technologies. These Deep-submicron (DSM) designs are bringing new fault types which cannot be detected with traditional stuck-at test techniques. These faults can only be detected with at-speed and bridging tests which result in more test vectors leading to higher costs.

DFT MAX delivers push-button 10-100x test data and test time compression, thus enabling DSM testing for high fault coverage with no impact on test cost. Its unique Adaptive Scan technology generates an efficient scan architecture that delivers test compression with the smallest area. DFT MAX provides comprehensive, powerful design rule checking (DRC), including scan, boundary scan, test compression synthesis, integration and verification capabilities. It is transparently integrated within Synopsys’ Design Compiler® and the entire Galaxy™ Design Platform to achieve best timing closure and to eliminate costly iterations between design and test implementation without test expertise. It transparently supports all TetraMAX and TetraMAX DSMTest ATPG features and fault models, delivering the same very high quality test vectors and high accuracy failure diagnosis as the traditional scan methodology.

Key Benefits

• 10-100x test time and test volume reduction
• Same high test coverage and ease of use as traditional scan
• No impact on design timing
• No impact on design physical implementation
• Higher test quality for designs at 130-nm, 90-nm and below

DFT MAX Features

• Adaptive Scan technology delivers 10-100x test time and test volume reduction
• Built-in to synthesis, it’s as easy to implement as regular scan
• Integration with Design Compiler Topographical Technology and IC Compiler for concurrent optimization of area, power, timing, physical and test constraints
• Supports low power and multi-voltage flows
• Complete Test DRC analysis at the Register Transfer Level (RTL) and gate level
• Hierarchical scan synthesis
• Boundary scan synthesis and compliance checking to the 1149.1 standard
• Transparent integration with TetraMAX ATPG

Figure 1: DFT MAX Compiler delivers 10-100X test time and test volume reduction

Figure 2: DFT MAX - Adaptive Scan technology

Adaptive Scan Technology Delivers 10-100x Test Time And Test Volume Reduction
As process technologies migrate to 130nm and below, many timing-related manufacturing defects occur, and cannot be detected with stuck-at tests alone. Additional tests that target transition delay, path delay and bridging faults are needed to improve quality. Because these tests increase the total number of patterns by 5-10x, they can lead to a substantial increase in tester time and may even exceed available ATE memory resources.

DFT MAX reduces the costs of nanometer testing by providing 10-100x test data volume compression (Figure 1) within design synthesis. Using an innovative “Adaptive Scan” architecture, DFT MAX saves test time and makes it possible to include DSMTest patterns in tester configurations where memory is limited. With the industry’s most area-efficient solution, DFT MAX has virtually no impact on design timing and results in the same high test coverage using TetraMAX ATPG as traditional scan (Figure 2 ).

Test Compression Synthesis
DFT MAX is an extension of the existing test synthesis flow in DFT Compiler. It synthesizes scan and test compression directly from RTL to testable gates with full optimization of synthesis design rules and constraints. All test and compression requirements specified prior to the synthesis process are met concurrently with area, timing and power optimization. It creates a gate-level implementation with all scan design rules checked and all test and compression logic verified, leading to very high and predictable test coverage and test compression results. The implementation of DFT, including test compression, within the design synthesis environment allows problems to be found and fixed earlier in the design cycle, thus avoiding ‘schedule-killing’ design iterations. DFT MAX also has an interface to TetraMAX ATPG to transparently deliver the test architecture specification to the test pattern generation engine and seamlessly generates compressed test patterns delivering the highest test quality.

Figure 3: Physical-aware test compression synthesis flow

Integration With Galaxy Design Platform For Concurrent Optimization Of Area, Power, Timing, Physical And Test Constraints
In Synopsys’ unique synthesis flow (Figure 3), “Adaptive Scan” logic is synthesized at the same time as scan chain architecting and stitching within the Galaxy implementation platform. Topographical scan chain ordering and partitioning provides excellent timing and area correlation with physical results using IC Compiler. This enables designers to achieve area, power, timing and DFT closure simultaneously. DFT MAX generates a SCANDEF file with detailed scan chain information which IC Compiler uses to perform further optimization to reduce area impact and decrease overall routing congestion (Figure 4).

Figure 4: These screen captures show how Adaptive Scan offers the same design timing,
no congestion, same test coverage and 10-100x-test time reduction as traditional scan.

Complete DFT Rules Checking From RTL To Gate Level
DFT MAX enables designers to create “test-friendly” RTL. It identifies DFT rules violations early in the design cycle during the pre-synthesis stage and avoids design iterations. From RTL to gate level, the DFT rules checker validates that the design is compliant with scan rules leading to operational scan chains and the highest test coverage. The violations can be debugged through a graphical browser in Design Vision. Its comprehensive set of rules checks for:

• Violations that prevent proper scan operation
• Violations that prevent data capture
• Violations that lower fault coverage

The same DRC engine is run from RTL to gate level and ATPG, making it possible for designers to validate testability all the way through the design synthesis process.

Hierarchical Scan Synthesis
To handle the test synthesis of large designs, some level of abstraction is required so that the System/Chip Integrator can reduce design time. By abstracting the DFT information in a test-model, along with timing and placement information, DFT MAX enables quick hierarchical test implementation of multi-million gate designs.

Boundary Scan Synthesis And Compliance Checking To The 1149.1 Standard
DFT MAX delivers a complete set of boundary scan capabilities including:

• TAP and BSR synthesis
• Compliance checking to the IEEE 1149.1 standard
• Boundary Scan Description Language (BSDL) file generation
• Functional and DC parameters vectors generation for manufacturing test

Figure 5: Adaptive Scan fully supports proven TetraMAX ATE links
for an effective and accurate yield diagnosis solution.

Transparent Integration With TetraMAX Power-Aware ATPG
DFT MAX transfers all information about the Adaptive Scan architecture to TetraMAX to automatically generate compressed, power-aware test patterns with highest test coverage. Adaptive Scan supports all existing TetraMAX ATPG algorithms and DSMTest fault models.

Integration With TetraMAX Diagnostics
Adaptive Scan fully supports proven TetraMAX ATE links for failure diagnosis and delivers a straightforward flow from tester fail to location of the defect. DFT MAX and TetraMAX Diagnostics together deliver a very effective and accurate yield diagnosis solution (Figure 5).