HAPS®-60 series of FPGA-Based Prototyping Systems 

HAPS®-60 Series of High-performance FPGA-Based Prototyping Systems 

FPGA-Based Prototyping Made Easy
The HAPS-60 series is an easy-to-use and cost effective FPGA-based prototyping system. The HAPS-60 series enables early hardware/software integration and system-level validation at near-real-time run-rates, using at-speed, real-world interfaces.

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HAPS-60 series highlights:
  • Accelerates development of complex SoCs
  • Shortens time-to-market
  • Reduces design and development risk
  • Significantly enhances economics of SoC design
  • Extensive portfolio of daughter boards available

HAPS-64 FPGA-Based Prototyping System

What's new...
Enhancements to the HAPS system technology, as well as the use of the latest Xilinx Virtex®-6 FPGAs, provide designers using the HAPS-60 series with superior capacity, performance, and advanced verification modes. The HAPS-60 series enables SoC designers to build next generation designs faster, with less risk, and more profitably.

For more information on the HAPS-60 series contact your local Synopsys sales office or send an email to fpga-based-prototyping@synopsys.com.

HAPS-60 Features:
  • Xilinx Virtex-6 LX760 FPGAs
  • High performance Time Division Multiplexing (TDM)
  • High speed connectors with I/O performance up to 30% faster
  • Advanced use modes including co-simulation, transaction-based verification, Universal Multi-Resource Bus (UMRBus)
  • Advanced power and cooling management
HAPS-60 Benefits:
  • Highest Performance: Achieving clock frequencies of up to 200MHz, the HAPS-60 series supports applications requiring real-time interfaces such as video, cellular data or live network traffic. The HAPS-60 series, which runs up to 30 percent faster than the previous generation, incorporates performance enhancing technologies that are not available on other solutions. This technology advantage enables full system integration and testing of all hardware and software in a real-world environment. Software developers benefit by being able to write, execute and debug code in a near real-time system-level environment, enabling the early identification and elimination of hardware and software bugs months ahead of silicon availability.
  • Highest Capacity: The flexible architecture of HAPS systems, combined with advanced high-capacity partitioning software and new automated high-speed Time Division Multiplexing (HSTDM), allow the HAPS-60 series to achieve greater capacities than other prototyping systems. This capacity advantage allows design teams to build prototypes of very large systems on chips (SoCs). A single HAPS system can support designs up to 18M ASIC gates (more than double the capacity of the previous generation), and multiple boards can be connected together for higher capacity.
  • Pre-tested IP: With many of the DesignWare® IP cores such as SuperSpeed USB 3.0, PCI Express® and HDMI pre-tested on HAPS systems, designers benefit from having a proven solution for system-level hardware and software prototyping using the same SoC production RTL. Using the same RTL from prototype to production reduces project schedule – and risk. With pre-tested DesignWare IP, project leaders using HAPS systems can focus their engineering resources on product differentiation and system validation instead of verifying the IP portions of their prototype.
  • Advanced verification functionality: The HAPS-60 series provides advanced verification functionality, previously unavailable in prototyping systems, enabling engineers to reduce verification time by using the HAPS-60 series hardware early in the design cycle. Built on Synopsys’ high-performance Universal Multi-Resource Bus (UMRBus) technology, new modes of verification include co-simulation through standard PLI and SCE-MI 2.0 transaction interfaces with Synopsys VCS and Innovator products, C/C++ programs, and other event driven simulators.
HAPS-Specific Design Planning Features
Synopsys' Certify ASIC prototyping software is tightly integrated with the Synopsys HAPS Family of FPGA-based prototyping hardware to ease design planning tasks. In addition to the features to ease RTL code conversion and ASIC design partitioning across multiple FPGAs, tight integration of HAPS systems allows Synopsys to offer unique solutions for HAPS:
  • Plan and implement HAPS boards immediately with Certify's extensive library of motherboard and daughter board descriptions
  • Quickly bring-up multi-board HAPS system prototypes with Tcl-based system target scripting
  • Eliminate FPGA I/O congestion by sharing Xilinx Virtex high-speed pin pairs of HAPS-60 systems
  • Obtain highly accurate prototype performance reviews of HAPS-60 systems with multi-chip, system-level static timing analysis
HAPS-Specific Connectivity and Debug Features
Synopsys' Identify RTL debugger, HAPS-60 Co-Sim & TBV Suite, and HAPS UMRBus (Universal Multi-Resource Bus) Interface Kit connects HAPS to a host workstation for system monitoring, RTL debug, and advanced verification. In addition to the features to ease RTL debugging of single FPGAs, tight integration of HAPS systems allows Synopsys to offer unique solutions for high capacity debug and system connectivity:
  • Apply a HAPS Deep Trace Debug SRAM daughter board for 100X signal visibility over traditional FPGA logic debuggers
  • Improve prototype state visibility by data streaming between HAPS and a host workstation with HAPS UMRBus interface
  • Co-simulate with Synopsys VCS to ease the migration of SoC blocks to the FPGA-based prototype
  • Stimulate the DUT executing in HAPS from the host side by a C/C++, SystemC, or SystemVerilog based testbench for a high-performance transaction-based verification (TBV) flow
Troubleshoot and Debug Made Easier
Click here to find additional information on HAPS Deep Trace Debug and other Synopsys tools that can help troubleshoot your FPGA-based prototype and quickly isolate RTL bugs.

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