This course covers the ASIC synthesis flow using Design Compiler. You will learn how to read, constrain and synthesize a complex design for area and timing. You will learn how to analyze the synthesis results and generate output data for downstream layout tools. The course is targeted at ASIC digital designers with little to no Design Compiler experience. Full Course Description
In this course you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. Full Course Description
In this course you will use Power Compiler to analyze and optimize average power consumption at the RT and gate levels. You will also use RTL Power Estimator to perform pre-synthesis average power estimation. Full Course Description
