| Formality |
Students will use Formality to perform formal equivalence checking on designs that have been transformed in various ways. For example, students will verify that a gate-level and an RTL-level design are equivalent and that a gate-level design and an ECO’d gate-level design are equivalent.
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| HSPICE Essentials |
This course covers the essentials of using HSPICE including how to set up and run a simulation, and how to perform AC, DC and transient analyses. Topics include simulation algorithms, file structure, HSPICE components and syntax, viewing simulation output and more.
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| HSPICE Advanced Topics |
This course covers using HSPICE for statistical analysis and signal integrity applications. Topics include advanced components and syntax, statistical analysis using Monte Carlo, using the field solver and, extracting S-parameters using linear analysis.
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| HSIM |
This course will teach you how to use the Synopsys HSIM FastSpice simulator.
It will introduce HSIMplus, a comprehensive platform for simulation and analysis of high performance analog, mixed-signal, memory, and system on-chip designs including important post-layout effects.
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| MAST Modeling |
The MAST Modeling course will give the student the ability to use Saber more effectively by explaining how to parameterize existing models, how to develop macro models, how to develop simple device models, and how to develop an understanding of general device models.
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| Nanosim |
The course teaches you the basics of the NanoSim engine, and how to set up and run a simulation. NanoSim is a superset of TimeMill and PowerMill, and includes all features available in those two tools.
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| NanoTime and NanoTime Ultra |
This course takes you from the introduction of fundamental concepts through advanced features of NanoTime and NanoTime Ultra for transistor-level static timing, including the usage of scripts to convert PathMill runs to NanoTime. The objective of this workshop is to provide the user the ability to use NanoTime and NanoTime Ultra to perform static timing analysis on large blocks, create .lib models for use in hierarchical analysis, and run signal integrity delay analysis.
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| SystemVerilog Assertions (SVA) |
This course teach the key features of the SystemVerilog Assertion (SVA) language and its use in VCS. You will learn how to write immediate and concurrent assertions and the use of sequences in assertions to make them reusable. Assertion coverage and use of cover properties to assess the effectiveness of your testbench is also covered.
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| SystemVerilog Testbench |
This course provides the skills required to deploy advanced functional verification techniques. Concepts covered include SystemVerilog language syntax, constrained random stimulus generation, coding style recommendations, object oriented programming concepts, functional coverage and verification methodology (VMM) introduction.
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| SystemVerilog Verification using VMM Methodology |
In this course, you will learn to apply the VMM Methodology using SystemVerilog language. It teaches how to use VMM base classes to build a testbench that can implement any test with minimal or no modification. It is recommended to take SystemVerilog Testbench workshop before this class.
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| Saber |
This course teaches engineers how to use the Saber Designer mixed-signal and mixed-technology suite of tools: Saber Sketch, Saber Simulator and CosmosScope.
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| Vera |
This course reinforces the verification concepts taught in lecture through a series of intense labs. At the end of this class, students should have the skills required to write an object-oriented OpenVera testbench to verify a device under test with coverage-driven random stimulus using VCS and Vera.
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| OpenVera RVM |
In this course, you will learn to effectively use the Verification Methodology Manual (VMM) based RVM classes. You will learn how to use these RVM classes to build a testbench environment to implement any test with minimal or no modification. This course requires OpenVera knowledge, and is typically taken after the Vera 1 workshop.
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