High-Reliability Design: No Room for Error 

Achieve Functional Safety and Highly Reliable Design

Synopsys Synplify® Premier software offers FPGA designers an automated means to build into their design functional safety, high uptimes, and highly reliable design operation. These designs become resistant to radiation-induced errors and other single bit flips that might otherwise result in incorrect operation or, even, system lock-up. As FPGA device geometries shrink, this solution is becoming a “must have” for systems deployed in industrial, medical, automotive, communications, military and aerospace applications.

Industry standards including DO-254, IEC 61508 and ISO 26262 define functional safety and error mitigation strategies for the creation and validation of high reliability systems. The Synplify Premier tool automates industry methods for mitigating soft errors such as single-event upsets (SEUs) that are increasingly present in the latest FPGA process geometries. Synplify Premier provides two essential elements to automate SEU immunity and create safe designs that operate with high reliability in radiation-rich environments.

  • Direct support for SEU error detection and recovery schemes across all FPGA device families from Altera, Lattice, Microsemi and Xilinx
  • Automated support for the creation of SEU error monitors, enabling software-based error mitigation schemes for controlling, monitoring, recovery and diagnostics of system errors that occurred due to SEUs


Using Synplify Premier, FPGA designers have multiple options for implementing error detection and mitigation circuitry, such as:

  • Memory protection by inferring error correcting code (ECC) memory primitives and by inserting triple modular redundancy (TMR) on Block RAMs to mitigate single-bit errors.
  • Safe FSM implementation that will force a state machine into a reset state or into a user-defined error state so the error can be handled in a specific way. The software can implement a “safe case FSM” which will ensure that, should the FSM enters an undefined state, it will recover, avoiding state machine lock-up.
  • Fault-tolerant FSMs with Hamming-3 encoding for detecting and correcting single-bit errors, thus allowing correct operation of the FSM to resume right away.
  • Creation of TMR, useful for protecting and correcting the operation of SRAM logic, registers, IP, routing, clocks, configuration bits, memories, routing fabric and I/Os, This includes:
    • Local TMR to protect registers
    • Distributed TMR to protect synchronous logic, configuration bits, or external I/Os
    • Block TMR to protect synchronous modules, IP, routing and clocks
    • TMR-based mitigation of errors in non-flushable circuits that contain synchronous feedback loops
    • Physical separation of the triplicates on the FPGA die for additional SEU protection

Synplify Premier can automatically create error monitors and error flags, accessible either externally or internally within the design. Coupled with the ability to tap any node via the FPGA I/O to facilitate probing or fault injection for verification, Synplify Premier helps to accelerate implementation and test of high reliability designs.

Synplify Premier includes the Identify in-system RTL debugger, which allows you to specify and debug targeted error conditions and states of interest and relate the system behavior back to the RTL.

Learn more about creating safe, highly reliable, high uptime designs with Synplify Premier:

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