The Identify® RTL debugger allows you to instrument RTL HDL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation – only much faster and with in-system stimuli.
The Identify RTL debugger allows you to designate sample triggers, navigate the design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code, the HDL Analyst® RTL View, or third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design.
- Key Features
- Support for Altera, Microsemi and Xilinx devices
- Ability to instrument and debug an advanced FPGA design directly from RTL source code
- Advanced trigger creation allows the viewing of desired design operation scenarios and probe specific nodes in the circuit
- Visibility into the internal design while operating at full speed
- Display of debug results superimposed on top of RTL source, RTL structural view, or with a waveform viewer
- Selectively view up to 8 distinct groups of internal nodes with a single Identify IICE during a debug session
- Synthesis and placement bypass option allows rapid instrumentation changes of Virtex-7/6/5 FPGA
- Compatible with Synopsys verification solutions Verdi3™ and Siloti for automated debug and visibility of FPGA-based prototypes
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Figure 1: Identify Debugger session with source code annotation of sample data
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Debug Where You Design – in RTL Source
The Identify software sets the standard for RTL debug using FPGA hardware. Adding probe and trigger points to a design is quickly accomplished by browsing the HDL source code and clicking on a signal name or line number at code branches of CASE and IF-THEN constructs. You can instrument multiple FPGAs of an ASIC prototype in the same manner using Synopsys Certify® multi-FPGA ASIC prototyping software. Background integration with the Identify Intelligent In-Circuit Emulator (IICE) logic requires no direct source code modifications.
During FPGA device operation, capture results in real-time. Extract sample data using the standard JTAG port interface and display graphically as waveforms or source code annotations. Identify software automatically converts FPGA circuit-level signals back into the vectors and enumerated data types used in your RTL HDL source.
Isolate Design Faults Fast
The Identify RTL debugging software improves your productivity during system debug sessions with flexible trigger and sample methods that help isolate design faults. The Identify tool's programmable triggering makes it easy to detect even the most complex system behaviors. Triggers can be defined as simply as a signal matching a particular state or as complex as a having multiple signals complete a sequence of states over time. The Identify tool's sample methods allow you to record internal system state in various ways whenever a trigger occurs: snapshot a period of time around a trigger, snapshot only after some multiple of trigger events, or program a watchdog timer to snapshot whenever it expires. Combining the Identify tool's sampling and trigger expressions dramatically decreases the amount of data history you need to review during FPGA debug. And the Identify tool's extensive Tcl command language helps automate regression tasks.
Figure 2: Identify programmable state machine triggering
Upgrade Your FPGA Debugging Environment
The Identify tool's RTL debugging solution is a significant upgrade from external test equipment or first generation integrated logic analyzer (ILA) cores. While Logic Analyzers and Mixed Signal Oscilloscopes (MSOs) have high capacity and flexible triggering, they require precious FPGA I/Os to probe internal signals, require hand modifications to your design to route internal signals to the outside, and provide no means to relate internal circuit signal names back to your RTL source. First generation programmable ILA cores that are instantiated into your design have the same drawbacks as manual probing and can only support a debugging perspective from a post-synthesis, netlist level. If you are prototyping an ASIC design using multiple FPGAs, your RTL can be instrumented directly prior to partitioning by Identify software. Prototyping design flows that use FPGA ILAs require instrumentation after the partition step and so do not survive design revisions.