Synplify Premier® is the industry's most advanced FPGA design and debug environment. The Synplify synthesis tools provide fast runtime, performance, area optimization for cost and power reduction, multi-FPGA vendor support, incremental and team-design capabilities for faster FPGA design development. Synplify Premier includes features that automate the creation of highly reliable designs such as those used in medical, automotive, industrial automation, communications, military and aerospace applications.
Premier includes Identify Instrumentor to provide an easy-to-use method for finding functional errors in FPGA designs that are operating on the board. The solution offers simulator like visibility into the implemented FPGA hardware and view actual signal values from an operating FPGA, directly superimposed on RTL code. In this way, users can perform in-system debug at the target operating speed.
Premier is designed to accept optimized RTL, 3rd party, and internally/previously developed IP allowing broad design exploration and faster implementation.
In addition, Synplify integrates support for DesignWare® IP, Identify RTL Debugger, VCS® high-performance functional verification and an ASIC compatible synthesis flow for the creation of FPGA-based prototypes.
Synplify Pro and Premier Datasheet
- The Synplify Premier features:
- Automated gated clock conversion for FPGA-based prototyping support
- Integrated Identify RTL Debugger to quickly find functional errors
- Automated design for high reliability and safety-critical design including DO-254, ISO 26262 and IEC 61508
- Integration with VCS Simulator and direct support for DesignWare IP
- Best quality of results (QoR) for timing performance and area/cost reduction
- Distributed synthesis with support for single or multiple machine synthesis
- Accelerated runtimes delivering up to 3X runtimes with support for up to 4 processors per license
- Automatic memory and DSP inferencing provides optimal area, power and timing quality of results
- Broad language support with VHDL, Verilog, SystemVerilog, VHDL-2008 and mixed language synthesis
- Advanced design debug and diagnosis through HDL Analyst and hierarchical debug flows
For a detailed comparison of the features available in each tool, see the Synplify Feature Comparison Chart