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An Efficient Hierarchical Verification Flow for Low Power Designs

Adopting a new flow called SAM (Static Abstract Model) for hierarchical verification can provide guaranteed QoR by retaining enough logic needed for hierarchical modules while the performance of the runs would be much better than flat runs. Additionally, this flow enables the top-level integrator to focus on top-level violations only; integration related issues need not worry about violations deep inside hierarchical blocks since the block owners would sign-off their blocks after review of the violations. In this Synopsys webinar, we will cover the benefits of SAM flow, such as the 8X-15X runtime performance gain and reduced memory consumption compared to the full flat verification, all while not losing any QoR and greatly reducing TAT during low power verification sign-off.

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