Verification Videos
Faster Bug-Free Clock Gating Verification with VC Formal
In today's world, power efficient devices are a necessity and no longer a "nice to have". Designers are driven to reduce power consumption for their designs using many techniques, including effective insertion of clock gating logic. With the introduction of clock gating cells and corresponding logic, it is required to compare the RTL models before and after power optimization. Traditionally, rerunning the entire simulation tests were necessary, but this approach is time consuming and non-exhaustive. Formal Logic Equivalence Checking (LEC), initially appears to be a good fit but these solutions cannot verify sequential modifications.
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