Success Story + -

Success Stories

• Iontra Doubles Development Speed of Next-Gen Battery Charging Tech Using Synopsys Cloud SaaS
• Synaptics: Migrates ARC HS58x3 with QIK & DSO.ai
• Gowin and Synopsys Software-based PUF IP Success Story
  
• Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip

Articles & Blogs + -

Articles & Blogs

• Why SRAM PUF Technology Is the Bedrock of Dependable Security in Any Chip
• Synopsys Introduces Industry’s First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs
• Ultra Ethernet Consortium Set to Enable Scaling of Networking Interconnects for AI and HPC
• Synopsys-TSMC Successful Tapeout of a Test Chip Featuring a Multi-Die Design Using TSMC’s CoWoS Technology
• Synopsys Powers World’s Fastest UCIe-Based Multi-Die Designs With New IP Operating at 40 Gbps

 

Synopsys Webinars + -

Synopsys Webinars

• Synopsys and Altera, an Intel Company, Present: A Data-Driven Approach to Multi-Die Design Architecture
• UCIe Standard vs. UCIe Advanced: What Designers Need to Know

White Papers + -

White Papers

• Enabling Efficient Multi-Die Design Implementation and IP Integration
• Why HPC Chip Designers are Looking into Linear Pluggable Optics

Videos + -

Videos

• SRAM Physical Unclonable Functions (PUFs) and their benefits for Security
• Synopsys 40G UCIe IP Product Update
• Synopsys & Ashling - RISC-V Development Tools
• Synopsys & IAR Systems - Embedded Workbench for RISC-V
• Synopsys & LDRA - LDRA Tool Suite Demo with ARC-V Processor IP
• Synopsys & Tasking - FREERTOS Running on ARC-V
• Synopsys & Lauterbach - Trace32 Development Tool on ARC-V

News + -

News

• Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design
• Synopsys Powers World’s Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps