Interconnect Models

Generic:​

• SBL-TLM2-FT (AXI)​

• SBL-GCCI (ACE)​

Arteris​

• Arteris FlexNoC & Ncore​

Arm

• Arm Performance Models​

• Arm AHB/APB​

Synopsys​

• Synopsys AXI

Memory Subystems

Generic: ​

• Multiport memory controller (GMPMC)​

• SRAM controller​

• Cache controller​

• NoC​

Synopsys​

• uMCTL2 / DDR5/ LPDDR5 / HBM3 Memory Controller​

​RTL Co-simulation

Traffic, Processors, RTL

Task-based and trace-based workload models​

Cycle accurate processor ​

• ARC​

• Tensilica​

• CEVA​

​RTL Co-simulation/emulation