Mar 26, 2024/3 min read Reducing Errors and Iterations with an Enhanced Timing Constraints Signoff Flow By Naveen Battu, Rimpy Chugh Tags: Static Verification, Product Spotlight, Chip Design Insights, Verification, Formal Verification
Mar 08, 2024/9 min read SoC Design and Verification Solutions for a New Era of AI Chips By Kiran Vittal Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification
Oct 01, 2023/7 min read Synopsys Users & Experts Come Together Again for Annual VC Formal SIG Event By Yann Antonioli Tags: Verification Central, Verification, Formal Verification
Jul 12, 2023/2 min read Streamline Projects with Verdi and VCS Coverage Tools By Taruna Reddy Tags: Verification Central, Debug, Simulation, Verification, Formal Verification
Jun 25, 2023/3 min read AI & Math Core Verification: Datapath Validation By Jin Zhang Tags: Verification Central, Verification, Formal Verification
May 08, 2023/6 min read How to Shift Verification Left in Low-Power Chip Design By Avinash Palepu Tags: Static Verification, Product Spotlight, Chip Design Insights, Energy-Efficient SoCs, Verification, Formal Verification
Nov 20, 2022/4 min read How Formal Verification Tools Enhance SoC Simulation Coverage By Jin Zhang Tags: Product Spotlight, Chip Design Insights, Simulation, Verification, Formal Verification
Nov 09, 2022/5 min read How to Protect Advanced Chip Designs from Security Breaches By Ian Land Tags: Aerospace & Government, Silicon Lifecycle Management, Prototyping, Chip Design Insights, Simulation, Design, Emulation, Silicon IP, Verification, Formal Verification
Aug 23, 2022/5 min read Power-Aware Clock Domain Crossing with STMicroelectronics By Deepak Ahuja, Navneet Kumar Chaurasia Tags: Customer Spotlight, Static Verification, Chip Design Insights, Verification, Formal Verification
Jul 12, 2022/4 min read Enhancing Chip Verification with AI & Machine Learning By Rob van Blommestein Tags: Multi-Die System, Static Verification, AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, HPC, Data Center, Verification, Formal Verification
Jun 21, 2022/5 min read Formal Verification Services Ramp Up SoC Design Productivity By Jin Zhang Tags: Chip Design Insights, Verification, Formal Verification
May 10, 2022/7 min read Leveraging Static Linting Tools - ASIC Design Challenges By Rohit Kumar Ohlayan, Rimpy Chugh Tags: Static Verification, Chip Design Insights, Verification, Formal Verification
Nov 15, 2021/6 min read Formal Chip Design Verification in the Cloud: EDA Tools By Pratik Mahajan, Ahmed Elzeftawi Tags: Cloud, Chip Design Insights, Verification, Formal Verification
Nov 10, 2021/7 min read Advancing Women in Tech Careers: Q&A with Latha Venkatachari By Synopsys Editorial Staff Tags: Debug, Chip Design Insights, Verification, Inside Synopsys, Formal Verification
Oct 26, 2021/7 min read ASIC Hardware Verification: Debug Challenges & Solutions By Kiran Vittal Tags: Debug, Prototyping, Chip Design Insights, Emulation, Verification, Virtual Prototyping, Formal Verification
Jul 06, 2021/5 min read How Emulation Helps Find Power Bugs During SoC Verification By Alex Wakefield Tags: Static Verification, Chip Design Insights, Simulation, Design, Emulation, Energy-Efficient SoCs, Signoff, Verification, Virtual Prototyping, Formal Verification
Feb 23, 2021/5 min read Verifying Complex Datapath Designs with HECTOR By Kiran Vittal, Alfred Koelbl, Pratik Mahajan Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification
Jun 19, 2018/2 min read Managing Initial State in Formal Verification for Optimal Results By Synopsys Editorial Staff Tags: Verification, Formal Verification
Aug 16, 2017/1 min read Phalanx Strategy: Applying Greek Warfare Tactics to Formal Property Verification By Synopsys Editorial Staff Tags: Verification, Formal Verification