Advanced Processors Enable Seamless Human-Machine Interfaces for Virtual Reality

By: Michael Thompson, Product Marketing Manager, Synopsys

Today we are in the early stages of the transition to virtual reality, but soon you might have to pinch yourself to know if your surroundings are real or virtual. We currently see virtual environments used mostly in games, but this will change over the next few years as our interactions with electronics become more seamless and natural. The underlying hardware that will make this possible is advanced microprocessors that deliver very high levels of performance while staying within low power budgets, and are designed to handle the special tasks required for advanced human-machine interfaces. As a result, our connection and ease of access to information and one another, as well as our ability to interact with the digital world, will increase exponentially. 

Virtual reality is an artificial environment that is presented in a way that enables us to accept it as real even though we know it is not. As the experience becomes more immersive, it is easier for us to suspend disbelief. For example, if you have to use a mouse or pointing device to move around in a virtual world it will be much less natural than if you can use hand gestures. Creating seamless and natural interfaces is not easily done. It takes a lot more processing power and orders of magnitude more sophisticated processors to recognize hand gestures than the input from a pointing device. We are currently in the infancy of virtual technology and our connection is largely through hardware, like keyboards, mice and other pointing devices (Figure 1). This is beginning to change to more interpretive interfaces like touch, swipe, and voice. Ultimately the interface will be more natural, recognizing gestures, our mood, gaze, and other ambient cues that will drive an immersive and personal experience. 

Figure 1: The evolution of interaction
(Deloitte University Press, 24 Feb 2016. Kunkel et al. https://dupress.deloitte.com/dup-us-en/focus/tech-trends/2016/augmented-and-virtual-reality.html)

As designers conceptualize and build the technology for the future of human-machine interfaces, they are relying on embedded microprocessors that deliver levels of performance that were unthinkable just a few years ago and at surprisingly low levels of power consumption. In the past it was possible to just crank up the clock speed to get more performance, but realistically we have reached a limit of 2 GHz – 3 GHz, so new designs are being developed with multiple processors to achieve the required performance. However, simply increasing the number of processors to meet application processing requirements is limited by power consumption and area restrictions. Fundamentally, the ideal processors will be designed to maximize performance while minimizing power consumption, memory requirements and system resources. The days of throwing transistors at the problem to get higher performance are past. Performance efficiency is a key design metric for designers paying attention to energy per cycle and mW per mm², and not just performance.

To accomplish this, processors for human-machine interfaces will need provide higher processing performance without exceeding power budgets. Synopsys’ DesignWare® ARC® HS Processor Family, designed for high-end embedded applications with performance efficiency as a primary design metric, offers 2.5 GHz performance on 16-nm process, delivering more than 5200 DMIPS per core, using less than 50 mW of power. This is more than twice the performance and lower power consumption levels of other processors in this class; in some cases the processor can deliver more performance with less than half the power consumption of comparable processors.

To address the needs of today’s most innovative products, the ARC HS processors are available in dual-core and quad-core versions that support very high performance with symmetric or distributed processing. To enable additional design optimization, the processors are configurable so that each instance on a system-on-chip (SoC) can be tailored to the specific performance, power and area requirements of the application. Designers can also add their own custom instructions to the processor through the ARC Processor EXtension (APEX) interface to further increase performance, lower power consumption, or to add differentiating features to their design.