Cloud native EDA tools & pre-optimized hardware platforms
By Phani Emani, Suresh Venkatachalam, Sriram Balasubramanian, Sreenath Panganamala, Synopsys
Modern systems-on-chips (SoC) are becoming more complex with a larger number of CPUs and advanced GPUs to support a wide range of applications with additional peripheral managers and subordinates to meet the market demands. In any SoC-based subsystem, managers are broadly classified as latency-sensitive managers (e.g., CPUs), bandwidth-sensitive managers (e.g., GPUs) and best-effort managers (e.g., SATA and USB interfaces). These managers communicate with a shared memory controller (DDR) subordinate device.
In a SoC-based on-chip communication systems, the managers communicate with different subordinates through the interconnect fabric. The interconnect plays a vital role in routing traffic between the managers and subordinates. The access time to the bus (i.e., the time until the bus is granted) for latency-sensitive managers (CPU) and bandwidth requirements for bandwidth-sensitive managers (GPU) are key factors in determining the overall performance in a SoC, while accessing a shared memory controller subordinate.
AMBA® AXI™ is a high-performance SoC bus protocol. Synopsys’ DesignWare® IP for AMBA Interconnect (DW_axi) is an interconnect fabric implementation of AMBA 3 AXI/AMBA 4 AXI protocol. The DW_axi supports different arbitration schemes while routing the traffic between managers and subordinates. These arbitration schemes are used to distribute the bandwidth and control the latency requirements of the managers. However, these arbitration schemes are not enough to meet requirements of the managers.
The AMBA 4 AXI protocol brings in quality of service (QoS) signaling on the AXI bus to address the challenges imposed by bandwidth and latency requirements of various IP in a SoC.
By using the QoS feature, the average bandwidth requirements of different managers can be met by distributing the subordinate’s bandwidth amongst the managers in a fair mechanism to improve the SoC’s performance. The QoS feature also helps designs meet the average latency requirements of latency-sensitive managers.
Consider the subsystem in Figure 1, consisting of different types of managers (latency-sensitive manager, bandwidth-sensitive manager, and best-effort manager) and a shared-memory subordinate. The DW_axi interconnect connects the managers and subordinate.
Figure 1: Subsystem without QoS
Interconnect needs to meet the requirements of all types of managers, including the bandwidth requirements of the GPU, latency requirements of the CPU, and the requirements of the USB manager.
The subordinate’s bandwidth is fixed. For example, if the subordinate is a DDR memory, it can only support limited bandwidth based on the data width and frequency of operation.
Consider the following situations:
Implementing QoS will address these issues.
The purpose of QoS in the interconnect is to regulate and prioritize the incoming traffic so that the latency and bandwidth requirements are met for all types of managers.
Considering the conditions described previously, adding QoS to the interconnect improves performance:
The QoS in DW_axi is designed to meet the requirements of all types of managers in a sub-system. Synopsys’ QoS solution is illustrated Figure 2.
Figure 2: QoS in DesignWare IP for AMBA Interconnect
The QoS controller in DW_axi is comprised of a QoS bandwidth regulator and a QoS arbiter.
The QoS regulator regulates the rate of the incoming traffic on the address channel of a manager port. The QoS regulator can be configured on each of the manager ports per address channel, i.e., each write and/or read address channel. If the incoming traffic is more than the desired rate, the QoS regulator will limit the traffic.
The QoS arbiter prioritizes the requests based on the priority value. The QoS arbiter can be configured on each of the subordinate ports per address channel, i.e., each write and/or read address channel. The QoS arbiter ensures that high-priority requests are serviced first to meet the requirements of latency-sensitive managers.
The memory controller (DDR) bandwidth is fixed for a given frequency of operation and data bus width. The QoS regulator on the manager port will regulate the incoming traffic at a manager port, which lends predictability to the sharing of the subordinate’s bandwidth by different managers. The QoS regulator can be programmed on each manager port, per address channel separately, according to the bandwidth requirements of the manager. The requests from the manager, on each address channel, will be regulated based on the programmed rate. The QoS Arbiter will prioritize the high priority requests, thereby meeting the latency requirements of latency-sensitive managers.
The following DW_axi features are fully configurable and can be selected when configuring the core in coreConsultant or coreAssembler.
The DesignWare IP for AMBA Interconnect is packaged as a .run file. Designers use the Synopsys coreConsultant tool to configure, synthesize, simulate, and verify the IP configuration. The image also includes:
For more information, visit www.synopsys.com/AMBA.