Synopsys DDR2/3-Lite Protocol Controller IP

The Synopsys DDR2/3-Lite SDRAM Protocol Controller IP Core (PCTL) offers an efficient digital interface between a single on-chip interface and a DDR2 or DDR3 physical layer (PHY) in a DDR2/3 memory subsystem. The Synopsys Protocol Controller provides efficient DDR control and protocol translation without the need of full featured memory controller functions such as multiple application ports, quality of service (QoS) control and optimized memory read/write transaction reordering (often referred to as scheduling).

The PCTL is developed for use with proprietary memory schedulers, enabling the implementation of unique traffic requirements. The PCTL takes a stream of pre-scheduled read and write commands thorough a single application port. It then converts them to DDR protocol and intelligently schedules the precharge, bank activate and refresh commands to optimize the memory channel bandwidth. The PCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training. Used together with the Synopsys DDR PHY Cores, the Synopsys DDR2 and DDR2/3-Lite IP solutions are the low risk, highest performance, and most easily integrated DDR2 and DDR2/3 solutions in the market.The DDR2/3-Lite PCTL is compatible with both Synopsys DDR2/DDR PHY IP (only supporting DDR2 mode) and the Synopsys DDR2/3-Lite PHY IP.

Synopsys DDR Complete Solution Datasheet