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DesignWare DDR2/3-Lite Protocol Controller IP

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The Synopsys DesignWare® DDR2/3-Lite SDRAM Protocol Controller IP Core (PCTL) offers an efficient digital interface between a single on-chip interface and a DDR2 or DDR3 physical layer (PHY) in a DDR2/3 memory subsystem. The DesignWare Protocol Controller provides efficient DDR control and protocol translation without the need of full featured memory controller functions such as multiple application ports, quality of service (QoS) control and optimized memory read/write transaction reordering (often referred to as scheduling).

The PCTL is developed for use with proprietary memory schedulers, enabling the implementation of unique traffic requirements. The PCTL takes a stream of pre-scheduled read and write commands thorough a single application port. It then converts them to DDR protocol and intelligently schedules the precharge, bank activate and refresh commands to optimize the memory channel bandwidth. The PCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training. Used together with the DesignWare DDR PHY Cores, the DesignWare DDR2 and DDR2/3-Lite IP solutions are the low risk, highest performance, and most easily integrated DDR2 and DDR2/3 solutions in the market.The DDR2/3-Lite PCTL is compatible with both DesignWare DDR2/DDR PHY IP (only supporting DDR2 mode) and the DesignWare DDR2/3-Lite PHY IP.

DesignWare DDR Complete Solution Datasheet
 

  • Provides a complete, single vendor DDR3/DDR2 SDRAM interface solution, when combined with the DesignWare DDR2/3-Lite PHY IP
  • Provides a complete DDR2 SDRAM interface solution when combined with the DesignWare DDR2/DDR PHY IP (only supports DDR2 mode)
  • Supports JEDEC-standard DDR3 and DDR2 protocols (JESD79-3 and JESD79-2, respectively)
  • Configurable 2:1 or 4:1 data width ratio from application bus to DDRn bus
    • 2:1 architecture with 533 MHz application bus max clock speed for up to 1066 Mbps DDRn
    • 4:1 architecture with 266 MHz application bus max clock speed for up to 1066 Mbps DDRn
  • Enables automatic translation of application bus reads/writes to bank interleaved DDR3/DDR2 protocol commands (precharge, activate, read, write)
  • Contains basic data training logic for supporting DesignWare DDR2/3-Lite and DDR2/DDR PHYs
  • Support for x8, x16, and x32 memories, for a total memory data path width of up to 72 bits
  • Support for partial population of memories, where not all DDRn byte lanes are populated with memory chips
  • Support for up to four memory ranks and up to 32 open memory banks
  • Programmable bank management policies: open-page, close-page
  • Three clock cycles best case command latency
  • 1T or 2T memory command timing
  • Automatic power-down entry and exit
  • Software driven self-refresh entry and exit
  • Optional ECC generation and checking for 32-bit and 64-bit memory bus widths
  • Optional in-line ECC bits, allowing for external processing of ECC bits
  • APB interface for PCTL software-accessible registers