Sensors are becoming increasingly ubiquitous. Many applications, such as the Internet of Things, automobiles, and mobile devices increasingly rely on the ability to read and interpret environmental conditions such as pressure, temperature, motion, and proximity. This is driving the development of more complex sensor SoCs. By pre-integrating sensor-specific IP blocks together with software in a single subsystem, Synopsys gives designers a complete, SoC-ready sensor control solution that can significantly reduce their design and integration effort, lower design risk and accelerate time-to-market.
The DesignWare® Sensor IP Subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more power efficient processing of the sensor data. The fully configurable subsystem consists of a DesignWare ARC® EM4 32-bit processor, serial digital interfaces, analog-to-digital converter interfaces, hardware accelerators, a comprehensive software library of DSP functions and I/O software drivers. The DesignWare Sensor IP Subsystem provides designers with a complete and pre-verified solution that meets the requirements of a broad range of applications such as such as intelligent sensors, sensor fusion, and sensor hub increasingly prevalent in automotive, mobile, industrial and smart energy markets.
Figure 1: DesignWare Sensor IP Subsystem integrated hardware and software solution
Introducing the DesignWare Sensor IP Subsystem Learn how the complete DesignWare Sensor IP Subsystem consisting of integrated and pre-verified hardware and software enables rapid integration of sensor functionality into SoCs.
Rich Collins Product Marketing Manager, IP Subsystems
Integrated, pre-verified hardware and software IP subsystem consisting of a power- and area-efficient ARC 32-bit processor, digital and analog interfaces, hardware accelerators, software library of DSP functions and I/O drivers
Highly configurable with tightly integrated peripherals and dedicated hardware maximize sensor processing efficiency
More than ten configurable hardware accelerators reduce memory footprint and decrease power consumption by a factor of 10 compared to equivalent discrete component implementations
Extensive library of off-the-shelf software DSP functions, including mathematical, filtering, matrix/vector and decimation/interpolation, speeds application software development
Implementations as small as 0.01mm2, consuming less than 4uW/MHz in a 28-nm process