Accelerate the Development of Mobile Device with New DesignWare MIPI IP

Synopsys expands the DesignWare MIPI IP portfolio with silicon-proven CSI-2 Host Controller, D-PHY and 3G DigRF.

DesignWare CSI-2 Host Controller

The MIPI CSI-2 interface provides a high speed, serial interface between a baseband processor or dedicated image processor and a CSI-2 compliant camera sensor. The CSI-2 specification has been developed by the MIPI Alliance to help reduce power consumption, EMI and development time of hand held devices with integrated cameras.

The DesignWare CSI-2 Host Controller is compliant with the latest MIPI CSI-2 specification and can be configured to handle 1 to 4 data lanes. Supporting data transfers from 80Mbps in Low Power mode to 1Gbps per lane in High Speed mode it provides a total throughput up to 4Gbps, enabling support for camera sensors with over 14 Mega-Pixels of resolution. The core handles all protocol management functions and provides multiple levels of error detection and correction. It supports multiple low power modes including shut down. The DesignWare CSI-2 host controller is fully configurable through Synopsys coreConsultant and designed to easily integrate with standard interfaces on both the system and PHY sides.

Combined with the DesignWare_APB_i2c and CSI-2 optimized DesignWare D-PHY Rx the DesignWare CSI-2 Host Controller is an ideal choice for implementing a robust, low power and high speed interface to CSI-2 capable camera sensors.

DesignWare D-PHY

The MIPI D-PHY is a high speed, scalable PHY used in multiple MIPI interfaces such as the Camera Serial Interface (CSI-2), the Display Serial Interface (DSI) and the universal chip to chip interface UniPro.

The DesignWare MIPI D-PHY is a fully integrated core implemented either with fully bidirectional lanes or as a Receive only configuration, optimized for CSI-2 Host or DSI Device implementations. Designed to conform to the latest MIPI D-PHY specification, it includes all the analog and digital circuitry delivered as a fully verified hard macro. It supports multiple low power mode including shut down and provides multiple test modes for increased reliability. The core implements the MIPI recommended Protocol Peripheral Interface (PPI) to ensure ease of integration with the protocol controller layer.

The DesignWare MIPI D-PHY provides a high-reliability high-speed differential interface reducing line count and minimizing cable wires and EMI shielding requirements and is an ideal solution for MIPI CSI-2, DSI and UniPro interfaces.

DesignWare 3G DigRF

MIPI DigRF v3 is a low-power, low pin-count serial interface that simplifies the integration and interoperability between the RF transceiver IC and baseband IC (BBIC). The six-pin digital interconnect reduces system cost and lowers Electromagnetic Interference (EMI) for dual and single-mode 3GPP 2.5/3G mobile terminals. With a maximum throughput of 312Mbps, the interface uses a simple frame based protocol applicable to 2.5G GPRS/EGPRS and release 5, 6 and 7 FDD UMTS including HSDPA, HSUPA with Rx diversity. The silicon-proven DesignWare 3G DigRF IP solution consisting of controllers for both Master and Slave, dual-mode PHY and verification environments is compliant with the latest standard specification and enables easy integration of the MIPI DigRF v3 standard in both digital baseband and RF ICs. The PHY includes an analog phase-locked loop (PLL) and is developed as a hard IP block to help ensure the integrity of the high-speed clocks and signals meet the strict timing requirements of the protocol.

Available in advanced 65- and 40-namometer (nm) process technologies, this high-quality solution has been implemented in multiple baseband and RF IC designs. The DesignWare 3G DigRF IP solution is based on the MIPI Alliance DigRF V3.09 specification and consists of DigRF Master and DigRF Slave controllers and a dual mode PHY.

DigRF v3.09 is a chip-to-chip communication protocol between the Digital Baseband IC and the Analog Baseband/RF IC, for 3GPP 3G/2.5G (UMTS/EGPRS) Mobile Terminals. The interface reduces the pin count required for interfacing BBIC and RFIC, reduces power consumption and increases interoperability. The DesignWare 3G DigRF IP solution is fully silicon-proven in multiple end user designs.

For information on the DesignWare MIPI IP solutions or additional products currently under development, please contact us.