Updates to TSMC Nexsys Libraries for the 65-nm and 90-nm Process Technology

A new release of TSMC Nexsys Standard Cells for the TSMC 65-nm LP process is now available to all DesignWare Library licensees. Available for Nominal, Low or High Vt, the libraries are optimized for low power design and enable power and performance tradeoffs. These new libraries have been re-characterized based on the latest spice model and provide support for multi-voltage island and coarse grain MTCMOS implementation.

A new release of the TSMC Nexsys Standard Cells libraries for TSMC 90G process is also available. The new libraries enable Coarse Grain MTCMOS implementation and provide CCS timing and noise models.

Finally, a new release of the TSMC Nexsys Standard Cells libraries for TSMC 90GT process is also available. This new release provides support for the latest design rules and Spice models. It also includes an additional set of high-speed flip-flops for improved performance. The standard cells are available in 3 different Vt versions.

These libraries complement the offering already available for TSMC 90-nm, 0.13-�m and 0.15-�m.