Complete 1.6T Ultra Ethernet IP Solution
The Synopsys 1.6T Ultra Ethernet IP solution, consisting of 1.6T MAC and PCS multi-rate Ultra Ethernet controllers, silicon proven 224G and 112G Ethernet PHY IP, and verification IP, is designed to meet the performance requirements of interconnects in the scale-out of AI Clusters compliant to the upcoming Ultra Ethernet Consortium specification. The solution is based on the evolving IEEE 802.3dj/df Ethernet standard with support of the Ultra Ethernet MAC and PHY layers for a GPU, NIC or scale-up Switch. The IP solution supports Interconnects at the rates of 400G, 800G and 1.6T.
By providing a complete IP solution, Synopsys delivers latency optimization and ensures that all the IP functions seamlessly together to lower integration risk. The high-bandwidth, excellent performance of the Ethernet IP solution is optimized for low power, small area and low latency.
The best-in-class IP solution has undergone thorough validation with various hardware platforms, PHYs, and Ethernet verification suites across a diverse range of processes and foundries. Leveraging Synopsys’ extensive PAM-4 design expertise and a proven track record in high-speed Ethernet controller designs, designers can accelerate time-to-market and achieve first pass silicon success for their advanced SoCs.
Complete 1.6T Ultra Ethernet IP Solution
- Ethernet MAC, PCS and PHY to complete a full Ultra Ethernet interface stack
- Supports evolving IEEE 802.3 and OIF-224G electrical standards
- Provides support for 4 x 400G, 2 x 800G, and 1.6T Ethernet rates using 112Gbps and 224Gbps SerDes
- Meets performance criteria for chip-to-chip, chip-to-module, and long reach copper/backplane interconnects
- Incorporates a DAC-based PAM-4 transmitter with feed-forward equalization (FFE)
- High-performance receiver equalization, supporting a channel loss up to 45dB
- Utilizes low jitter phase-locked loops (PLLs) for robust timing recovery and improved jitter performance
- Features a digital-based receiver with an analog front-end (AFE), ADC, and an advanced digital signal processor (DSP)
- Inserts and extracts Control Ordered Sets (CtlOS) required for Link-Level Retry and Credit Based Flow Control mechanisms
- Supports IEEE 1588 applications
- Includes Ethernet PCS RS-FEC functions • Compatible with IEEE-managed objects, IETF MIB II, and RMON for management applications