The Synopsys ARC® FastMath Pack for ARC HS processors is a set of hardware extensions and an accompanying set of software wrapper functions that provide a collection of additional instructions supporting a range of mathematical functions that can be used with all ARC HS processors. These include
The instructions support 16-bit and 32-bit data types. In addition to the extension instructions, the FastMath Pack includes a number of extension auxiliary registers.
All FastMath instructions are encoded in 32-bit formats and observe all of the established rules for encoding ARCv2 instructions for use with ARC HS processors. The instructions are implemented in the APEX extension space using the major opcode 0x07. In addition, all FastMath instructions and register names have the prefix “FMP_” to ensure they do not create any namespace clashes with existing ARCv2 instructions or other customer-defined instructions.
The FastMath instructions significantly reduce cycle count compared to the same functions implemented in software. They are easy to use and implemented as standard C-functions in application code.
Synopsys ARC FastMath Pack for ARC HS Processors
Description: | The FastMath Pack is a math processing accelerator for the ARC HS family |
Name: | dwc_arc_fastmath_pack_for_hs |
Version: | 4.10a |
ECCN: | 3E991/NLR |
STARs: | Open and/or Closed STARs |
myDesignWare: | Subscribe for Notifications |
Product Type: | DesignWare Cores |
Documentation: | |
Download: | arc_hs_processor |
Product Code: | B559-0 |