Synopsys ARC NPX6FS Neural Processors for Functional Safety

The ASIL B or D Ready Synopsys ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of Advanced Driver Assistance Systems (ADAS) and autonomous vehicle systems that require artificial intelligence (AI) for vision, RADAR, LiDAR and / or sensor fusion.

The NPX6FS NPUs include state-of-the-art hardware safety features including diagnostic error injection, windowed watchdog timers, error classification, and software diagnostic tests as well as safety monitors and lockstep capabilities for safety-critical modules. The processors include dedicated safety mechanisms for ISO 26262 compliance and address the mixed criticality and virtualization requirements of next-generation zonal architectures.

Comprehensive safety documentation, including safety manuals, FMEDA and DFMEA reports, accelerate SoC-level functional safety assessments. These features enable designers to achieve high levels of fault coverage as required for ASIL certifications without a significant effect on performance, power or area compared to the non-ASIL Ready NPX6 NPUs.

The NPX6FS NPUs are fully programmable and combine the flexibility of software solutions with the high performance and low power consumption of dedicated hardware.

The NPX6FS NPUs are supported by the ASIL D Ready ARC MetaWare MX Development Toolkit for Safety to help simplify the development of ISO 26262-compliant software.

There are multiple ARC NPX6 FS NPU IP products to choose from to meet specific application requirements. The architecture is based on individual cores. Either one 1K MAC core or 4K MAC cores that can scale from 4K MACs to 96K MACs for a single AI engine performance of over 250 TOPS (or over 440 TOPS with sparsity). NPX6 FS NPU IP includes hardware and software support for multi-NPU clusters of up to eight NPUs achieving 3500 TOPS with sparsity. Advanced bandwidth features in hardware and software, and a memory hierarchy (including L1 memory in each core and a high-performance, low latency interconnect to access a shared L2 memory) make scaling to a high MAC count possible. An optional tensor floating point unit is available for applications benefiting from BF16 or FP16 inside the neural network. An optional data compression is also available using microscaling formats (OCP MX data types) which reduces memory footprint and bandwidth pressures for large models.

Synopsys ARC NPX6FS NPU IP Family Datasheet