Security Options for ARC Processors
With the vast amount of personal data stored in the cloud and transferred between smart devices, it is increasingly important to have effective security measures in place to avoid the threat of data breaches and malicious attacks.
Enhanced Security Package Option for ARC EM Cores
The Enhanced Security Package option available for Synopsys ARC® EM Processors enables designers to create a tamper-resistant, secure environment that protects their systems and software from vulnerabilities using a single ultra-low power processor.
The option includes SecureShield™ technology to enable development of a trusted execution environment, reducing the area and power that an additional security core and associated memories would require. SecureShield technology protects critical processor registers like stack and instruction pointer registers as well as secure bus accesses, and includes a secure memory protection unit (MPU) to protect traditional instruction and data memory. The secure MPU has up to 16 configurable memory regions with the option for per region scrambling and encryption.
The Enhanced Security Package also consists of an encrypted, tamper-resistant pipeline and additional protection features such as data and instruction path integrity checks and watchdog timer to help prevent IP theft and system attacks.
Designers can also add user-defined instructions and co-processors through the ARC Processor EXtension (APEX) technology and restrict their operations to a secure mode, enabling IP protection throughout the value chain.
Enhanced Security Package Option for ARC HS Cores
The Enhanced Security Package option for ARC HS Processors enables designers to create a secure environment that protects their systems and software from evolving security threats such as IP theft and intentional remote attacks. The package includes the capability to protect critical processor registers like stack and instruction pointer registers as well as secure bus accesses and includes a memory protection unit (MPU) with up to 16 configurable memory regions to protect traditional instruction and data memory. Also included is data and instruction path integrity checks to prevent fault injection attacks, error detection codes (EDC) on memories and key registers, stack bounds checking and a watchdog timer.
As with the ARC EM processors, designers can add user-defined instructions and co-processors through the ARC Processor EXtension (APEX) technology for cryptographic or encryption purposes.
ARC CryptoPack Option for EM Cores
The Synopsys ARC® CryptoPack option provides the ability to speed up software encryption implementations by adding custom instructions and registers to the ARC EM processors using the ARC Processor EXtension (APEX) interface. Supported software algorithms include Advanced Encryption Standard (AES), Triple Data Encryption Standard (3DES ), Elliptic Curve Cryptography (ECC), Secure Hash Algorithm with 32-bit words (SHA-256) and Rivest-Shamir-Adleman (RSA) encryption.
ARC CryptoPack System Block Diagram
Synopsys ARC CryptoPack: Extensions for Cryptographic Software Acceleration Datasheet Enhanced Security Package for Synopsys ARC EM Processor Family Datasheet Enhanced Security Package for Synopsys ARC HS Processor Family Datasheet Intrinsic-ID Physically Unclonable Function (PUF) Solution for Synopsys ARC EM Processors
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| Secure Your IoT Device with Ultra-Low Power ARC Processors Learn how DesignWare ARC Processors help secure your IoT design without an extra security core, keeping area and power consumption to a minimum. Please download the white paper "Securing the Internet of Things: An Architect's Guide to Securing IoT Devices Using Hardware Rooted Processor Security" |
- Enhanced Security Package
- Includes SecureShield technology to enable a trusted execution environment
- Secure MPU with up to 16 configurable regions and per region scrambling/encryption capability
- In-line instruction and data encryption and address scrambling to protect algorithms from reverse engineering or IP theft
- Data and instruction path integrity checking to prevent fault injection attacks
- Integrated watchdog timer detects system failures that can result from tampering and enables counter measures
- Ability to add secure custom instructions or co-processors in a trusted mode boosts performance and reduces power
- CryptoPack
- Easy to add option for EM Family of processors
- Area-optimized and performance-optimized versions to scale to system goals
- Up to 7x or more speedup to perform cryptographic functions
- Supported cryptographic software algorithms
- AES
- 3DES
- ECC
- SHA-256
- RSA
| Description: | CryptoPack is a set of APEX based instructions to accelerate software cryptography algorithms on ARC EM processors |
| Name: | dwc_arc_em_cryptopack |
| Version: | 1.10a |
| ECCN: | 5D002.b2/ENC |
| STARs: | Open and/or Closed STARs |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | arc_em_cryptopack |
| Product Code: | B206-0 |
| Description: | Enhanced Security Package option for ARC EM Processors |
| Name: | dwc_arc_em_esp |
| Version: | 5.70a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | arc_em_processor |
| Product Code: | B754-0 |
| Description: | Enhanced Security Package option for ARC HS cores |
| Name: | dwc_arc_hs_esp_option |
| Version: | 4.10a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | arc_hs_processor |
| Product Code: | E038-0 |