Synopsys 56G Ethernet PHY IP

The Synopsys 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurement techniques, the 56G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3 and OIF standards electrical specifications. The PHY is small in area, low in power consumption, and high in performance, meeting the needs of chip-to-chip, chip-to-module (copper and optical), and copper backplane interconnects, down to 35dB channel loss.

The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4) and Non-Return-to-Zero (NRZ) signaling to deliver up to 400G Ethernet. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates with the Synopsys Physical Coding Sublayer and Digital Controllers/Media Access Controller (MAC) IP solutions to reduce design time and to help designers achieve first-pass silicon success.

Synopsys 56G Ethernet PHY IP Datasheet

 

Highlights
Products
Downloads and Documentation
  • Supports full-duplex 9.9 to 58Gbps data rates in 1, 2, and 4 lanes
  • Enables 50G, 100G, 200G, 400G Ethernet interconnects for wired network infrastructure
  • Supports IEEE 802.3 and OIF standards electrical specifications
  • Meets the performance requirements of chip-to-chip, chip-to-module, and backplane interconnects
  • DAC-based PAM-4 transmitter includes feed forward equalization (FFE)
  • Digital-based receiver consists of analog front-end (AFE), ADC, and digital signal processor (DSP)
  • High-performance receive equalization supports channel loss of 35dB
  • Continuous calibration and adaptation (CCA) provides robust performance across voltage, and temperature
  • Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance
56G Ethernet PHY, TSMC 12FFC x1, North/South (vertical) poly orientationSTARs Subscribe
56G Ethernet PHY, TSMC 12FFC x2, North/South (vertical) poly orientationSTARs Subscribe
56G Ethernet PHY, TSMC 12FFC x4, North/South (vertical) poly orientationSTARs Subscribe
56G Ethernet PHY, TSMC 16FFC x4, North/South (vertical) poly orientationSTARs Subscribe
Description: 56G Ethernet PHY, TSMC 12FFC x1, North/South (vertical) poly orientation
Name: dwc_56g_ethernet_phy_tsmc12ffc_x1ns
Version: 1.02a
ECCN: 5E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
Download: dwc_56g_ethernet_phy_tsmc12ffc_x1ns
Product Code: F825-0
Description: 56G Ethernet PHY, TSMC 12FFC x2, North/South (vertical) poly orientation
Name: dwc_56g_ethernet_phy_tsmc12ffc_x2ns
Version: P-46101A
ECCN: 5E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
Download: dwc_56g_ethernet_phy_tsmc12ffc_x2ns
Product Code: E883-0
Description: 56G Ethernet PHY, TSMC 12FFC x4, North/South (vertical) poly orientation
Name: dwc_56g_ethernet_phy_tsmc12ffc_x4ns
Version: 1.02a
ECCN: 5E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
Download: dwc_56g_ethernet_phy_tsmc12ffc_x4ns
Product Code: G829-0
Description: 56G Ethernet PHY, TSMC 16FFC x4, North/South (vertical) poly orientation
Name: dwc_56g_phy_tsmc16ffc_x4ns
Version: 1.01a
ECCN: 5E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
Download: dwc_56g_phy_tsmc16ffc_x4ns
Product Code: D228-0