The Synopsys DesignWare® DDR3/2 Protocol Controller Core (PCTL) offers an efficient digital interface between a single on-chip interface and a DDR3 or DDR2 physical layer (PHY) in a DDR3/2 memory subsystem. The DesignWare Protocol Controller provides efficient DDR control and protocol translation without the need of full featured memory controller functions such as multiple application ports, quality of service (QoS) control and optimized memory read/write transaction reordering (often referred to as scheduling).The PCTL is developed for use with proprietary memory schedulers, enabling the implementation of unique traffic requirements The PCTL takes a stream of pre-scheduled read and write commands in thorough a single application port. It then converts them to DDR protocol and intelligently schedules the precharge, bank activate and refresh commands to optimize the memory channel bandwidth. The PCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training. Used together with the DesignWare DDR3/2 PHY Cores and Verification IP, the DesignWare DDR3/2 IP solutions are the low risk, highest performance, and most easily integrated DDR3/2 solutions in the market.The DDR3/2 PCTL is compatible with all DesignWare DDR3/2 PHY IP.
DesignWare DDR3/2 IP Demo at 1600 Mbps Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.