The Synopsys DesignWare® DDR3/2 Protocol Controller Core (PCTL) offers an efficient digital interface between a single on-chip interface and a DDR3 or DDR2 physical layer (PHY) in a DDR3/2 memory subsystem. The DesignWare Protocol Controller provides efficient DDR control and protocol translation without the need of full featured memory controller functions such as multiple application ports, quality of service (QoS) control and optimized memory read/write transaction reordering (often referred to as scheduling).
The PCTL is developed for use with proprietary memory schedulers, enabling the implementation of unique traffic requirements The PCTL takes a stream of pre-scheduled read and write commands in thorough a single application port. It then converts them to DDR protocol and intelligently schedules the precharge, bank activate and refresh commands to optimize the memory channel bandwidth. The PCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training. Used together with the DesignWare DDR3/2 PHY Cores and Verification IP, the DesignWare DDR3/2 IP solutions are the low risk, highest performance, and most easily integrated DDR3/2 solutions in the market.The DDR3/2 PCTL is compatible with all DesignWare DDR3/2 PHY IP.
Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.
Provides a complete, single vendor DDR3/DDR2 SDRAM interface solution, when combined with the DesignWare DDR3/2 PHY IP
Supports JEDEC-standard DDR3 and DDR2 protocols (JESD79-3 and JESD79-2, respectively)
Support for JEDEC-standard DDR3 and DDR2 UDIMMs and RDIMMs
Up to 2133Mbps supported with a maximum 533MHz PCTL clock
PCTL architecture uses a 4:1 data width conversion from NIF to DDRn
Enables automatic translation of application bus reads/writes to bank interleaved DDR3/DDR2 protocol commands (precharge, activate, read, write)
Efficient DDR protocol implementation with in-order Read and Write commands and efficiently scheduled out-of-order Activate and Precharge commands
Integrated DDR3/2 PHY Utility Block (PUB) - Automated RTL algorithms for PHY initialization/calibration and production test (for use with PUB-compatible DWC DDR3/2 PHYs)
Support for x8, x16, and x32 memories, for a total memory data path width of up to 72 bits
Support for partial population of memories, where not all DDRn byte lanes are populated with memory chips
Support for up to four memory ranks and up to 32 open memory banks
Programmable bank management policies: open-page, close-page
Three clock cycles best case command latency
1T or 2T memory command timing
Automatic power-down entry and exit
Software driven self-refresh entry and exit
Optional ECC generation and checking for 32-bit and 64-bit memory bus widths
Optional in-line ECC bits, allowing for external processing of ECC bits
Dual PCTL mode available to support two independent memory channels using one time multiplexed address and command lane (significant pin count savings)
APB interface for PCTL software-accessible registers