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ECO Kits

The Engineering Change Order (ECO) extension library kits give designers the flexibility to create logic elements using metal only for cost-effective design changes. Designers can use these kits after a chip has been placed and routed to accommodate last minute product requirements or correct final verification issues.


SiWare Logic Libraries
Empty ECO sites can be filled with fill cells or DCAPs from base library

SiWare Logic Libraries
Empty ECO sites can be filled with fill cells or DCAPs from ECO Kit

Synopsys Foundation IP for TSMC 28HP Datasheet
Synopsys Foundation IP for TSMC 28HPM Datasheet

 

Highlights
Features
  • Easy to Use
    • Standard design flow
    • More flexible than spare gates
    • Characterized cells replace randomly placed filler cells or DCAP cells
    • Can be clustered in special row or column areas
    • Characterized with same VTs, PVTs as base libraries
  • Cost Effective
    • Only metal and contact layers
    • Wafers held at contact can be finished quickly for time to market
  • Rich Cell Set
    • Base array filler cells
    • Pre-characterized metal programmable macros
    • Combinational, sequential and support cells
    • Multiple drive strengths
  • Combinatorial (and bubble versions)
    • Inverter, buffer
    • Simple gates - NAND, OR
    • Complex gates - NOR, XNOR
    • AOI/OAI
    • Mux/demux
  • Sequential (and scan versions)
    • Flip-flops - with clear and preset
    • Scan flip-flops
    • D-Type transparent latch
  • Support cells
    • Filler cells with and without decoupling capacitors


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