The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.

Synopsys offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.

Synopsys PHY IP for PCI Express 4.0 Datasheet

Highlights

Products

Downloads and Documentation

Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
Supports lane margining at the receiver
L1 substate and SRIS support
Power gating and power island
Embedded Bit Error Rate (BER) tester and internal eye monitor
Built-in Self Test vectors, PRBS generation and checker
IEEE 1149.6 AC JTAG Boundary Scan
Supports -40C to 125C junction temperatures
Supports flip-chip packaging

PCIe 4.0 PHY, SS 14LPU x4, North/South (vertical) poly orientation for Automotive AEC-Q100 Grade 1	STARs	Subscribe
PCIe 4.0 PHY, SS 8LPU x4, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 1	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N7 x1, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N7 x2, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2	STARs	Subscribe
20G PHY for PCIe 4 PHY, GF12LPP 1.8V x4, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, SS SF4E x2, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, SS SF4X x4, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, TSMCN3E 1.2V x1, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, TSMCN3E 1.2V x2, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, TSMCN3E 1.2V x4, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, TSMC N4P 1.2V x1, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, TSMC N4P 1.2V x2, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, TSMC N5 1.2V x1, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, TSMC5FF 1.2V x2, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4.0, TSMC N5 1.2V x4, North/South (vertical) poly orientation	STARs	Subscribe
Differential Buffer, TSMC N5, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, GF 12LP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, GF 12LP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, GF 12LP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, GF14LPP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, GF14LPP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS 11LPP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS 11LPP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS 11LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS14LPP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS 14LPP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS14LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS 14LPU x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS SF2, x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC16FFC x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC N7+ x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC N7 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N6 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N6 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N6 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N7RF x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N7 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N7 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N7 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 SR PHY, TSMC N2P x2, North/South (vertical) poly orientation	STARs	Subscribe

Description:	10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc7ff_ns
Version:	2.09a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer Databook for TSMC 7FF (PHY Version: 2.09a) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 7FF (PHY Version: 2.09a) ( TEXT )
Download:	dwc_diffbuf_tsmc7ff_ns
Product Code:	C522-0

Description:	20G PHY for PCIe 4 PHY, GF12LPP 1.8V x4, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_gf12lpp18_x4ns
Version:	2.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.30a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks Consumer 20 PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 PHY (PCS Version: 1.47v) ( PDF \| HTML ) DesignWare Cores PCIe4 PHY for GF12 LPP (PHY Version: 2.03a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe4 PHY for GF12 LPP Release Notes (PHY Version: 2.03a) ( TEXT )
Download:	dwc_c20pcie4phy_gf12lpp18_x4ns
Product Code:	F972-0

Description:	20G PHY for PCIe 4 PHY, SS SF4E x2, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_ss4lpe12_x2ns
Version:	2.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Hardware Emulation Application Note (Doc Version: 0.90a) ( PDF \| HTML ) High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00b) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP PCIe4 PHY ATE Testbench Application Note (Doc Version: 0.50a) ( PDF \| HTML ) Databooks PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 x4 PHY (PCS Version: 14.71a) ( PDF \| HTML ) Synopsys PHY IP Consumer 20 PCIe4 PHY for SS4LPE x2 (PHY Version: 2.05a) ( PDF \| HTML ) Reference Manuals Synopsys PHY IP Consumer 20 PCIe4 PHY for SS4LPE x2 Reference Manual (PHY Version: 2.05a) ( PDF \| HTML ) Synopsys PHY IP Consumer 20 PCIe4 PHY for SS4LPE x2 Reference Manual with Changes (PHY Version: 2.05a) ( PDF ) Release Notes Synopsys PHY IP PCIe 4.0 x2 NS for SS 4LPE 1.2V (PHY Version: 2.05a) ( TEXT )
Download:	dwc_c20pcie4phy_ss4lpe12_x2ns
Product Code:	H122-0

Description:	20G PHY for PCIe 4 PHY, SS SF4X x4, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_ss4lpp12_x4ns
Version:	2.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40a) ( PDF \| HTML ) Hardware Emulation Application Note (Doc Version: 0.90a) ( PDF \| HTML ) High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 20 PCIe4 PHY Reference Manual for SS4LPP x4 (PHY Version: 2.03a) ( PDF \| HTML ) DesignWare Cores Consumer 20 PCIe4 PHY for SS4LPP x4 (PHY Version: 2.03a) ( PDF \| HTML ) PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 x4 PHY (PCS Version: 14.72b) ( PDF \| HTML ) Release Notes DesignWare Cores Consumer 20 PCIe4 PHY for SS4LPP x4 Release Notes (PHY Version: 2.03a) ( TEXT )
Download:	dwc_c20pcie4phy_ss4lpp12_x4ns
Product Code:	G824-0

Description:	20G PHY for PCIe 4 PHY, TSMC N4P 1.2V x1, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc4ffp12_x1ns
Version:	2.02b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00b) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys Compilation Using the LC and FC End-User Platform (Doc Version: 2022.03) ( PDF \| HTML ) Synopsys PHY IP PCIe4 PHY ATE Testbench Application Note (Doc Version: 0.60a) ( PDF \| HTML ) Databooks Synopsys PHY IP C20 PCIe4 PHY for TSMC 4 FFP x1 Databook (PHY Version: 2.02b) ( PDF \| HTML ) Synopsys PHY IP PCIe4 PCS for PCIe4 PHY x1 Databook (PCS Version: 14.77c) ( PDF ) Reference Manual Synopsys PHY IP C20 PCIe4 PHY for TSMC 4 FFP x1 Reference Manual (PHY Version: 2.02b) ( PDF \| HTML ) Release Notes Synopsys PCIe4 PHY for TSMC 4 FFP x1 Release Notes (PHY Version: 2.02b) ( TEXT )
Download:	dwc_c20pcie4phy_tsmc4ffp12_x1ns
Product Code:	H074-0

Description:	20G PHY for PCIe 4 PHY, TSMC N4P 1.2V x2, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc4ffp12_x2ns
Version:	2.02b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00b) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys Compilation Using the LC and FC End-User Platform (Doc Version: 2022.03) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Synopsys PHY IP PCIe4 PHY ATE Testbench Application Note (Doc Version: 0.60a) ( PDF \| HTML ) Databooks Consumer 20 PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 PHY x2 (PCS Version: 14.77b) ( PDF \| HTML ) DesignWare® Cores Consumer 20 PCIe4 PHY for TSMC 4 FFP x2 (PHY Version: 2.02a_d1) ( PDF \| HTML ) DesignWare® Cores Consumer 20 PCIe4 Reference Manual for TSMC 4 FFP x2 (PHY Version: 2.02a) ( PDF \| HTML ) Release Notes DesignWare Cores Consumer 20 PCIe4 PHY for TSMC 4 FFP x2 Release Notes (PHY Version: 2.02a) ( TEXT )
Download:	dwc_c20pcie4phy_tsmc4ffp12_x2ns
Product Code:	H150-0

Description:	20G PHY for PCIe 4 PHY, TSMC N5 1.2V x1, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc5ff12_x1ns
Version:	2.08c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40a) ( PDF \| HTML ) High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys Compilation Using the LC and FC End-User Platform (Doc Version: 2022.03) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 20 PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 PHY (PCS Version: 14.77a) ( PDF \| HTML ) DesignWare Cores PCIe4 x1 PHY for TSMC 5 FF (PHY Version: 2.08a) ( PDF \| HTML ) DesignWare Cores PCIe4 x1 Reference Manual for TSMC 5 FF (PHY Version: 2.08a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe4 x1 PHY for TSMC 5 FF Release Notes (PHY Version: 2.08a) ( TEXT )
Download:	dwc_c20pcie4phy_tsmc5ff12_x1ns
Product Code:	E460-0

Description:	20G PHY for PCIe 4 PHY, TSMC5FF 1.2V x2, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc5ff12_x2ns
Version:	2.08c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40a) ( PDF \| HTML ) High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys Compilation Using the LC and FC End-User Platform (Doc Version: 2022.03) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 20 PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 PHY x2 (PCS Version: 14.77a) ( PDF \| HTML ) DesignWare Cores Consumer 20 PCIe4 PHY x2 for TSMC 5 FF (PHY Version: 2.08a) ( PDF \| HTML ) DesignWare Cores Consumer 20 PCIe4 Reference Manual x2 for TSMC 5 FF (PHY Version: 2.08a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe4 PHY x2 for TSMC 5 FF Release Notes (PHY Version: 2.08a) ( TEXT )
Download:	dwc_c20pcie4phy_tsmc5ff12_x2ns
Product Code:	E461-0

Description:	20G PHY for PCIe 4 PHY, TSMCN3E 1.2V x1, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc3eff12_x1ns
Version:	4.05c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40a) ( PDF \| HTML ) High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks Synopsys PHY IP Consumer 20 PCIe4 PHY for TSMC3eFF x1 Databook (PHY Version: 4.05c) ( PDF \| HTML ) Synopsys PHY IP PCIe4 PCS for PCIe4 PHY x1 (PCS Version: 2.08a) ( PDF \| HTML ) Reference Manual Synopsys PHY IP Consumer 20 PCIe4 PHY for TSMC3eFF x1 Reference Manual (PHY Version: 4.05c) ( PDF \| HTML ) Release Notes PCIe4 PHY for TSMC 3eFF 1.2V x1 Release Notes (PHY Version: 4.05c) ( TEXT ) User Guide Synopsys PHY IP PCIe4 PHY coreKit User Guide (Doc Version: 0.10c) ( PDF \| HTML )
Download:	dwc_c20pcie4phy_tsmc3eff12_x1ns
Product Code:	G247-0

Description:	20G PHY for PCIe 4 PHY, TSMCN3E 1.2V x2, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc3eff12_x2ns
Version:	4.05c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40a) ( PDF \| HTML ) High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys Compilation Using the LC and FC End-User Platform (Doc Version: 2022.03) ( PDF \| HTML ) Databooks PCIe4 PCS for the Synopsys PCIe4 PHY x2 (PCS Version: 2.08c) ( PDF \| HTML ) Synopsys PHY IP Consumer 20 PCIe4 PHY for TSMC3eFF x2 Databook (PHY Version: 4.05c) ( PDF \| HTML ) Reference Manual Synopsys PHY IP Consumer 20 PCIe4 PHY for TSMC3eFF x2 Reference Manual (PHY Version: 4.05c) ( PDF \| HTML ) Release Notes Synopsys PHY IP Consumer 20 PCIe4 PHY for TSMC3EFF 1.2V Release Notes (PHY Version: 4.05c) ( TEXT ) User Guide Synopsys PHY IP PCIe4 PHY coreKit User Guide (Doc Version: 0.10c) ( PDF \| HTML )
Download:	dwc_c20pcie4phy_tsmc3eff12_x2ns
Product Code:	G236-0

Description:	20G PHY for PCIe 4 PHY, TSMCN3E 1.2V x4, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc3eff12_x4ns
Version:	4.05c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40a) ( PDF \| HTML ) High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys Compilation Using the LC and FC End-User Platform (Doc Version: 2022.03) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Synopsys PHY IP PCIe4 PCS for PCIe4 PHY x4 (PCS Version: 2.08a) ( PDF \| HTML ) Synopsys PHY IP PCIe4 PHY for TSMC 3eFF x4 Databook (PHY Version: 4.05c) ( PDF \| HTML ) Reference Manual Synopsys PHY IP PCIe4 PHY for TSMC 3eFF x4 Reference Manual (PHY Version: 4.05c) ( PDF \| HTML ) Release Notes PCIe4 PHY for TSMC 3eFF 1.2V x4 Release Notes (PHY Version: 4.05c) ( TEXT ) User Guides Synopsys PHY IP PCIe4 PHY coreKit User Guide (Doc Version: 0.10c) ( PDF \| HTML ) Synopsys PHY IP PCIe4 PHY coreKit User Guide (Doc Version: 0.10d) ( PDF \| HTML )
Download:	dwc_c20pcie4phy_tsmc3eff12_x4ns
Product Code:	G235-0

Description:	20G PHY for PCIe 4.0, TSMC N5 1.2V x4, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc5ff12_x4ns
Version:	2.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40a) ( PDF \| HTML ) High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys Compilation Using the LC and FC End-User Platform (Doc Version: 2022.03) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 20 PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 PHY x4 (PCS Version: 14.77a) ( PDF \| HTML ) DesignWare Cores PCIe4 PHY for TSMC 5 FF (PHY Version: 2.08a) ( PDF \| HTML ) DesignWare Cores PCIe4 Reference Manual for TSMC 5 FF (PHY Version: 2.08a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe4 PHY for TSMC 5 FF Release Notes (PHY Version: 2.08a) ( TEXT )
Download:	dwc_c20pcie4phy_tsmc5ff12_x4ns
Product Code:	E462-0

Description:	Differential Buffer, TSMC N5, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc5ff_ns
Version:	3.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer for TSMC 5FF (PHY Version:3.07a_d1) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 5FF (PHY Version: 3.07a) ( TEXT )
Download:	dwc_diffbuf_tsmc5ff_ns
Product Code:	F690-0

Description:	PCIe 4.0 LP PHY, TSMC N6 x1, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc6ff_x1ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x1 for TSMC 6FF Databook (PHY Version: 1.05a) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY One-Lane (PCS Version: 1.54a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x1 for TSMC 6FF Release Notes (PHY Version: 1.05a) ( TEXT )
Download:	dwc_pcie4_lp_phy_tsmc6ff_x1ns
Product Code:	E989-0

Description:	PCIe 4.0 LP PHY, TSMC N6 x2, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc6ff_x2ns
Version:	1.06a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 6FF Databook (PHY Version: 1.05a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 6FF Databook (PHY Version: 1.06a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 6FF Reference Manual (PHY Version: 1.06a) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY x2 (PCS Version: 1.54a) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY x2 (PCS Version: 1.57a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 6FF Release Notes (PHY Version: 1.05a) ( TEXT ) DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 6FF Release Notes (PHY Version: 1.06a) ( TEXT )
Download:	dwc_pcie4_lp_phy_tsmc6ff_x2ns
Product Code:	E990-0

Description:	PCIe 4.0 LP PHY, TSMC N6 x4, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc6ff_x4ns
Version:	1.06b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Synopsys PHY IP PCIe 4.0 LP PHY x4 for TSMC 6FF Databook (PHY Version: 1.06b) ( PDF \| HTML ) Synopsys PHY IP PCIe 4.0 LP PHY x4 for TSMC 6FF Reference Manual (PHY Version: 1.06b) ( PDF \| HTML ) Synopsys PHY IP PCS for the PCIe4 LP PHY x4 TSMC 6FF PHY/PCS Wrapper Databook (PCS Version: 1.55a) ( PDF \| HTML ) Release Notes Synopsys PHY IP PCIe 4.0 LP PHY x4 for TSMC 6FF Release Notes (PHY Version: 1.06b) ( TEXT )
Download:	dwc_pcie4_lp_phy_tsmc6ff_x4ns
Product Code:	E991-0

Description:	PCIe 4.0 LP PHY, TSMC N7 x1, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc7ff_x1ns
Version:	1.05b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x1 for TSMC 7FF Databook (PHY Version: 1.05b) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY One-Lane (PCS Version: 1.54a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x1 for TSMC 7FF Release Notes (PHY Version: 1.05b) ( TEXT )
Download:	dwc_pcie4_lp_phy_tsmc7ff_x1ns
Product Code:	H233-0

Description:	PCIe 4.0 LP PHY, TSMC N7 x1, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
Name:	dwc_ap_pcie4_lp_phy_tsmc7ff_x1ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP AP PHY x1 for TSMC 7FF Databook (PHY Version: 1.05a) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY One-Lane (PCS Version: 1.54a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP AP PHY x1 for TSMC 7FF Release Notes (PHY Version: 1.05a) ( TEXT )
Download:	dwc_ap_pcie4_lp_phy_tsmc7ff_x1ns
Product Code:	H670-0

Description:	PCIe 4.0 LP PHY, TSMC N7 x2, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc7ff_x2ns
Version:	1.05b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores Compilation Using the LC and FC End-User Platform 16G LP (Doc Version: 1.00a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 7FF Databook (PHY Version: 1.05b) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY (PCS Version: 1.55a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 7FF Release Notes (PHY Version: 1.05b) ( TEXT )
Download:	dwc_pcie4_lp_phy_tsmc7ff_x2ns
Product Code:	E231-0

Description:	PCIe 4.0 LP PHY, TSMC N7 x2, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
Name:	dwc_ap_pcie4_lp_phy_tsmc7ff_x2ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databooks DesignWare® Cores PCIe 4.0 LP AP PHY x2 for TSMC 7FF Databook (PHY Version: 1.05a) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY (PCS Version: 1.55a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP AP PHY x2 for TSMC 7FF Release Notes (PHY Version: 1.05a) ( TEXT )
Download:	dwc_ap_pcie4_lp_phy_tsmc7ff_x2ns
Product Code:	H317-0

Description:	PCIe 4.0 LP PHY, TSMC N7 x4, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc7ff_x4ns
Version:	1.05b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x4 for TSMC 7FF Databook (PHY Version: 1.05b) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY (PCS Version: 1.48a, March 26, 2021) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY (PCS Version: 1.54a_d1) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x4 for TSMC 7FF Release Notes (PHY Version: 1.01a_C4) ( TEXT ) DesignWare® Cores PCIe 4.0 LP PHY x4 for TSMC 7FF Release Notes (PHY Version: 1.05b) ( TEXT )
Download:	dwc_pcie4_lp_phy_tsmc7ff_x4ns
Product Code:	E232-0

Description:	PCIe 4.0 LP PHY, TSMC N7RF x1, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc7ffrf_x1ns
Version:	1.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Download:	dwc_pcie4_lp_phy_tsmc7ffrf_x1ns
Product Code:	H517-0

Description:	PCIe 4.0 PHY, SS14LPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss14lpp_x4ns
Version:	1.05b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist (Doc Version: 1.00) ( PDF ) DesignWare® Cores PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.15a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 Four-Lane PHY for SS 14 LPP Databook (PHY Version: 1.05b) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (PCS Version: 1.41) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for SS 14 LPP Release Notes (PHY Version: 1.05b) ( TEXT )
Download:	dwc_pcie4phy_ss14lpp_x4ns
Product Code:	C998-0

Description:	PCIe 4.0 PHY, GF 12LP x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_gf12lp_x1ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe4 PHY ATE Testbench (Doc Version:1.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe4 PHY for GF 12LP x1 Databook (PHY Version: 1.01a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (PCS Version: 1.48b, March 18, 2021) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe4 PHY x1 for GF 12LP Release Notes (PHY Version: 1.01a) ( TEXT )
Download:	dwc_pcie4phy_gf12lp_x1ns

Description:	PCIe 4.0 PHY, GF 12LP x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_gf12lp_x2ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe4 PHY ATE Testbench (Doc Version:1.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe4 PHY for GF 12LP x2 Databook (PHY Version: 1.01a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (PCS Version: 1.48b, March 18, 2021) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe4 PHY x2 for GF 12LP Release Notes (PHY Version: 1.01a) ( TEXT )
Download:	dwc_pcie4phy_gf12lp_x2ns

Description:	PCIe 4.0 PHY, GF 12LP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_gf12lp_x4ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe4 PHY ATE Testbench (Doc Version:3.0) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe4 PHY for GF 12LP x4 Databook (PHY Version: 1.01a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (PCS Version: 1.41, July 27, 2020) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe4 PHY x4 for GF 12LP Release Notes (PHY Version: 1.01a) ( TEXT )
Download:	dwc_pcie4phy_gf12lp_x4ns
Product Code:	E414-0

Description:	PCIe 4.0 PHY, GF14LPP x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_gf14lpp_x1ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Description:	PCIe 4.0 PHY, GF14LPP x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_gf14lpp_x2ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Description:	PCIe 4.0 PHY, SS 11LPP x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss11lpp_x1ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Download:	dwc_pcie4phy_ss11lpp_x1ns
Product Code:	E150-0

Description:	PCIe 4.0 PHY, SS 11LPP x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss11lpp_x2ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Download:	dwc_pcie4phy_ss11lpp_x2ns
Product Code:	E151-0

Description:	PCIe 4.0 PHY, SS 11LPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss11lpp_x4ns
Version:	1.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databook DesignWare® Cores PCIe 4.0 Four-Lane PHY for SS 11 LPP Databook (PHY Version: 1.00a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for SS 11 LPP Release Notes (PHY Version: 1.00a) ( TEXT )
Download:	PCIe-40-PHY_SS_11LPP_x4
Product Code:	E101-0

Description:	PCIe 4.0 PHY, SS 14LPP x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss14lpp_x2ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Databook DesignWare® Cores PCIe 4.0 Two-Lane PHY for SS 14 LPP Databook (PHY Version: 1.05a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Two-Lane PHY for SS 14 LPP Release Notes (PHY Version: 1.05a) ( TEXT )
Download:	PCIe-40-PHY_SS_14LPP_x2
Product Code:	E097-0

Description:	PCIe 4.0 PHY, SS 14LPU x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss14lpu_x2ns
Version:	1.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databooks PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY x2 Databook (PCS Version: 1.56a) ( PDF \| HTML ) Synopsys PHY IP PCIe 4.0 PHY for SS 14 LPU Databook (PHY Version: 1.00a) ( PDF \| HTML ) Reference Manual Synopsys PHY IP PCIe 4.0 PHY for SS 14LPU Reference Manual (PHY Version: 1.00a) ( PDF \| HTML ) Release Notes Synopsys PHY IP PCIe 4.0 Two-Lane PHY for SS 14 LPU Release Notes (PHY Version: 1.00a) ( TEXT )
Download:	dwc_pcie4phy_ss14lpu_x2ns
Product Code:	I607-0

Description:	PCIe 4.0 PHY, SS 14LPU x4, North/South (vertical) poly orientation for Automotive AEC-Q100 Grade 1
Name:	dwc_ag1_pcie4phy_ss14lpu18_x4ns
Version:	3.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook Synopsys PHY IP PCIe4 PHY for SS14LPU Databook AG1 (PHY Version: 3.01a) ( PDF \| HTML ) Release Notes Synopsys Automotive Grade 1 PCIe 4.0 PHY for SS 14LPU x4 Release Notes (PHY Version: 3.01a) ( TEXT )
Download:	dwc_ag1_pcie4phy_ss14lpu18_x4ns

Description:	PCIe 4.0 PHY, SS 8LPU x4, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 1
Name:	dwc_ap1_pcie4phy_ss8lpu18_x4ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
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Description:	PCIe 4.0 PHY, SS SF2, x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_sssf2_x4ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
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Description:	PCIe 4.0 PHY, SS14LPP x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss14lpp_x1ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Databook DesignWare® Cores PCIe 4.0 One-Lane PHY for SS 14 LPP Databook (PHY Version: 1.05a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 One-Lane PHY for SS 14 LPP Release Notes (PHY Version: 1.05a) ( TEXT )
Download:	PCIe-40-PHY_SS_14LPP_x1
Product Code:	E096-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x1ns
Version:	1.06b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databooks DesignWare Cores PCIe 4.0 PHY x1 for TSMC 12 FFC Databook (PHY Version: 1.06b) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY PHY/PCS Wrapper Databook (PCS Version: 1.41a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe 4.0 PHY x1 for TSMC 12 FFC Release Notes (PHY Version: 1.06b) ( TEXT )
Download:	dwc_pcie4phy_tsmc12ffc_x1ns
Product Code:	E201-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x16, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x16ns
Version:	1.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Sixteen-Lane PHY for TSMC FFC Release Notes (PHY Version: 1.03b) ( TEXT )
Download:	PCIe-40-PHY_TSMC_12FFC_x16
Product Code:	C667-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x2ns
Version:	1.06b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.17a) ( HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Synopsys PHY IP PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.17a) ( PDF ) Databooks DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 12FFC x2 Databook (PHY Version: 1.06b) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY Databook (April 15, 2021) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 12FFC x2 Release Notes (PHY Version: 1.06b) ( TEXT )
Download:	dwc_pcie4phy_tsmc12ffc_x2ns
Product Code:	C736-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x4ns
Version:	1.06b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.15a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 12 FFC Databook (PHY Version: 1.06b_d1) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY Databook (PCS Version: 1.41) ( PDF ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 12 FFC Release Notes (PHY Version: 1.06b) ( TEXT )
Download:	dwc_pcie4phy_tsmc12ffc_x4ns
Product Code:	C727-0

Description:	PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffpgl_x16ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.11a) ( PDF ) DesignWare® Cores Multi-Protocol 16G PHY RX Internal Eye Monitor (February 2017) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 Sixteen-Lane PHY for TSMC 16 FFPGL Databook (PHY Version: 1.03a) ( PDF ) DesignWare® Cores PCIe 4.0 Sixteen-Lane PHY for TSMC 16 FFPGL Registers with Change Bars (PHY Version: 1.03a) ( PDF ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (February 7, 2018) ( PDF ) Release Notes DesignWare® Cores Multi-Protocol 16G PHY Sixteen-Lane for TSMC 16 FFPGL Release Notes (PHY Version: 1.03a) ( TEXT )
Download:	PCIe-40-PHY_TSMC_16FFPGL_x16
Product Code:	C365-0

Description:	PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffpgl_x4ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.11a) ( PDF ) DesignWare® Cores Multi-Protocol 16G PHY RX Internal Eye Monitor (February 2017) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF \| HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFPGL Databook (PHY Version: 1.03a) ( PDF ) DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFPGL Registers with Change Bars (PHY Version: 1.03a) ( PDF ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (February 7, 2018) ( PDF ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFPGL Release Notes (PHY Version: 1.03a) ( TEXT )
Download:	PCIe-40-PHY_TSMC_16FFPGL_x4
Product Code:	B894-0

Description:	PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffpgl_x8ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.11a) ( PDF ) DesignWare® Cores Multi-Protocol 16G PHY RX Internal Eye Monitor (February 2017) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF \| HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 Eight-Lane PHY for TSMC 16 FFPGL Databook (PHY Version: 1.03a) ( PDF ) DesignWare® Cores PCIe 4.0 Eight-Lane PHY for TSMC 16 FFPGL Registers with Change Bars (PHY Version: 1.03a) ( PDF ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (February 7, 2018) ( PDF ) Release Notes DesignWare® Cores Multi-Protocol 16G Eight-Lane PHY for TSMC 16 FFPGL Release Notes (PHY Version: 1.03a) ( TEXT )
Download:	PCIe-40-PHY_TSMC_16FFPGL_x8
Product Code:	B895-0

Description:	PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc28hpcp_x2ns
Version:	3.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 28 HPCP Databook (PHY Version: 3.04a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY Databook (PCS Version: 1.41; PHY Version: 3.04a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 28 HPCP Release Notes (PHY Version: 3.04a) ( TEXT )
Download:	dwc_pcie4phy_tsmc28hpcp_x2ns
Product Code:	D478-0

Description:	PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc28hpcp_x4ns
Version:	3.02b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.11) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databook DesignWare® Cores PCIe 4.0 PHY x4 for TSMC 28 HPCP Databook (PHY Version: 3.02b) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 28 HPCP Release Notes (PHY Version: 3.02b) ( TEXT )
Download:	PCIe-40-PHY_TSMC_28HPCP_x4
Product Code:	C503-0

Description:	PCIe 4.0 PHY, TSMC N7 x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc7ff_x1ns
Version:	1.13a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe4 Single-Lane PHY for TSMC 7FF Databook (PHY Version: 1.13a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY x1 (Doc Version: 1.51b) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe4 Single-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.13a) ( TEXT )
Download:	dwc_pcie4phy_tsmc7ff_x1ns
Product Code:	E202-0

Description:	PCIe 4.0 PHY, TSMC N7+ x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc7ff_plus_x4ns
Version:	1.09a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databook DesignWare® Cores PCIe4 Four-Lane PHY for TSMC 7FFP Databook (PHY Version: 1.09a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe4 Four-Lane PHY for TSMC 7FFP Release Notes (PHY Version: 1.09a) ( TEXT )
Download:	PCIe-40-PHY_TSMC_N7P_x4
Product Code:	D818-0

Description:	PCIe 4.0 PHY, TSMC16FFC x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffc_x1ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.17a) ( HTML ) Synopsys PHY IP PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.17a) ( PDF ) Databooks PCIe 4.0 PCS for the Synopsys PHY IP PCIe 4.0 PHY x1 for TSMC 16FFC PHY/PCS Wrapper Databook (PCS Version: 1.57a) ( PDF \| HTML ) Synopsys PHY IP PCIe 4 PHY x1 for TSMC 16 FFC Databook (PHY Version: 1.10a) ( PDF \| HTML ) Reference Manual Synopsys PHY IP PCIe 4 PHY x1 for TSMC 16 FFC Reference Manual (PHY Version: 1.10a) ( PDF \| HTML ) Release Notes Synopsys PHY IP PCIe 4 PHY x1 for TSMC 16FFC Release Notes (PHY Version: 1.10a) ( TEXT )
Download:	dwc_pcie4phy_tsmc16ffc_x1ns
Product Code:	E200-0

Description:	PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffc_x2ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks PCIe 4.0 PCS for the Synopsys PHY IP PCIe 4.0 PHY x2 for TSMC 16FFC PHY/PCS Wrapper Databook (PCS Version: 1.57a) ( PDF \| HTML ) Synopsys PHY IP PCIe 4 PHY x2 for TSMC 16 FFC Databook (PHY Version: 1.10a) ( PDF \| HTML ) Reference Manual Synopsys PHY IP PCIe 4 PHY x2 for TSMC 16 FFC Reference Manual (PHY Version: 1.10a) ( PDF \| HTML ) Release Notes Synopsys PHY IP PCIe 4 PHY x2 for TSMC 16FFC Release Notes (PHY Version: 1.10a) ( TEXT )
Download:	dwc_pcie4phy_tsmc16ffc_x2ns
Product Code:	C665-0

Description:	PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffc_x4ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.40a) ( PDF \| HTML ) Synopsys PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.17a) ( HTML ) Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF \| HTML ) Synopsys PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Synopsys PHY IP PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.17a) ( PDF ) Databooks PCIe 4.0 PCS for the Synopsys PHY IP PCIe 4.0 PHY x4 for TSMC 16FFC PHY/PCS Wrapper Databook (PCS Version: 1.57a) ( PDF \| HTML ) Synopsys PHY IP PCIe 4 PHY x4 for TSMC 16 FFC Databook (PHY Version: 1.10a) ( PDF \| HTML ) Reference Manual Synopsys PHY IP PCIe 4 PHY x4 for TSMC 16 FFC Reference Manual (PHY Version: 1.10a) ( PDF \| HTML ) Release Notes Synopsys PHY IP PCIe 4 PHY x4 for TSMC 16FFC Release Notes (PHY Version: 1.10a) ( TEXT )
Download:	dwc_pcie4phy_tsmc16ffc_x4ns
Product Code:	C159-0

Description:	PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc7ff_x2ns
Version:	1.13a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe4 Two-Lane PHY for TSMC 7FF Databook (PHY Version: 1.13a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (Doc Version: 1.51b) ( HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY x2 (Doc Version: 1.51b) ( PDF ) Release Notes DesignWare® Cores PCIe4 Two-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.13a) ( TEXT )
Download:	dwc_pcie4phy_tsmc7ff_x2ns
Product Code:	E125-0

Description:	PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc7ff_x4ns
Version:	1.14a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe4 PHY ATE Testbench (Doc Version: 0.50a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe4 Four-Lane PHY for TSMC 7FF Databook (PHY Version: 1.14a) ( PDF \| HTML ) DesignWare® Cores PCIe4 PHY x4 for TSMC 7FF Reference Manual (PHY Version: 1.14a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY x4 (Doc Version: 1.56a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe4 Four-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.14a) ( TEXT )
Download:	dwc_pcie4phy_tsmc7ff_x4ns
Product Code:	C417-0

Description:	PCIe 4.0 SR PHY, TSMC N2P x2, North/South (vertical) poly orientation
Name:	dwc_pcie4_sr_phy_tsmc2p12_x2ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
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