2024-09-09 19:24:02
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI, and networking applications. The PHY’s flexible architecture supports standard
and advanced package technologies and allows up to 12.9Tbps/mm of data to travel at data rates up to 40Gbps. It supports widely used AMBA protocols such as AXI and CHI C2C in streaming mode and standards-based protocols such
as PCI Express and CXL. The IP offers maximum performance with low BER, minimum latency, and implementation flexibility. Synopsys UCIe PHY IP delivers high energy efficiency with an optimized architecture using a single reference
clock feature, low-voltage signaling, and hardware-based initialization. The mission mode integrated signal integrity monitors and comprehensive test and repair capabilities ensure die, die-to-die, and multi-die package health from in-design to in-field. Robust die-to-die link operation is ensured with embedded training and calibration algorithms. The PHY is compliant with the latest release of the UCIe specification, ensuring successful interoperability between heterogeneous dies.
Synopsys UCIe PHY IP along with Synopsys Controller IP and Verification IP deliver a complete solution for die-to-die connectivity in multi-die packages.
Synopsys UCIe PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
- Supports standard packaging technologies such as organic substrate and laminate
- Hardware-based initialization & sideband vendor message support
- 100 MHz single reference clock architecture
- Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming
UCIe-S PHY for Standard Package (x16) in TSMC N5A, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2 | STARs |
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UCIe-S PHY for Standard Package (x16) in SS SF2, North/South Orientation | STARs |
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UCIe-S PHY for Standard Package (x16) in SS SF4X, North/South Orientation | STARs |
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UCIe-S PHY for Standard Package (x16) in SS SF5A, North/South Orientation | STARs |
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UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation | STARs |
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UCIe-S PHY for Standard Package (x16) in TSMC N4P, North/South Orientation | STARs |
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UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation | STARs |
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UCIe-S PHY for Standard Package (x16) in TSMC N6, North/South Orientation | STARs |
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UCIe-S PHY for Standard Package (x32) in TSMC N3P, East/West Orientation | STARs |
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UCIe-S PHY for Standard Package (x32) in TSMC N3P, North/South Orientation | STARs |
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UCIe-A PHY for Advanced Package (x64) in SS SF4X, North/South Orientation with 8collumn module configuration | STARs |
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UCIe-A PHY for Advanced Package (x64) in TSMC N5, East/West Orientation with 8collumn module configuration | STARs |
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UCIe-A PHY for Advanced Package (x64) in SS SF2, North/South Orientation | STARs |
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UCIe-A PHY for Advanced Package (x64) in TSMC N3E, North/South Orientation | STARs |
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UCIe-A PHY for Advanced Package (x64) in TSMC N5, North/South Orientation | STARs |
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Description: |
UCIe-A PHY for Advanced Package (x64) in TSMC N3E, North/South Orientation |
Name: |
dwc_ucie_4ta4_tsmc3eff12_ns |
Version: |
1.00a-cuint |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes Synopsys PHY IP UCIe CoWoS-S Interposer using 3DIC-Compiler Design Guidelines (Version 0.80a) ( PDF | HTML )
Databooks Synopsys PHY IP Universal Chiplet Interconnect Express (UCIe) Advanced Package PHY Utility Block (PUB) Databook (PUB Version 1.10a) ( PDF | HTML )
Synopsys PHY IP Universal Chiplet Interconnect Express - Advanced Package (UCIe-A) PHY for TSMC 3EFF Databook (PHY Version: 1.00a_cuint) ( PDF | HTML )
Implementation Guide Synopsys PHY IP Universal Chiplet Interconnect Express - Advanced Package (UCIe-A) PHY Implementation Guide (Version 1.10a) ( PDF | HTML )
Programming Guide Synopsys PHY IP Universal Chiplet Interconnect Express (UCIe) PHY Programming Guide (Version 0.80a) ( PDF | HTML )
Release Notes Synopsys PHY IP Universal Chiplet Interconnect Express - Advanced Package (UCIe-A) PHY for TSMC 3EFF Release Notes (PHY Version: 1.00a_cuint) ( TEXT )
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Download: |
dwc_ucie_4ta4_tsmc3eff12_ns |
Product Code: |
H341-0 |
Description: |
UCIe-S PHY for Standard Package (x16) in SS SF5A, North/South Orientation |
Name: |
dwc_ucie_1ts4_sssf5a_ns |
Version: |
1.00a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes Synopsys PHY IP UCIe CoWoS-S Interposer using 3DIC-Compiler Design Guidelines (Version 0.80a) ( PDF | HTML )
Synopsys PHY IP UCIe Signal Integrity and Power Integrity Training Guide Application Note (Version 0.50a) ( PDF | HTML )
Databooks Synopsys PHY IP Universal Chiplet Interconnect Express (UCIe) Standard Package PHY Utility Block (PUB) Databook (PUB Version 1.01a) ( PDF | HTML )
Synopsys PHY IP Universal Chiplet Interconnect Express - Standard Package (UCIe-S) PHY for SS5LPE Databook (PHY Version: 1.00a) ( PDF | HTML )
Implementation Guide Synopsys PHY IP Universal Chiplet Interconnect Express - Standard Package (UCIe-S) PHY Implementation Guide (Version 1.30a) ( PDF | HTML )
Programming Guide Synopsys PHY IP Universal Chiplet Interconnect Express (UCIe) PHY Programming Guide (Version 0.80a) ( PDF | HTML )
Release Notes Synopsys PHY IP Universal Chiplet Interconnect Express - Standard Package (UCIe-S) PHY for SS5LPE Release Notes (PHY Version: 1.00a) ( TEXT )
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Download: |
dwc_ucie_1ts4_sssf5a_ns |
Product Code: |
H741-0 |
Description: |
UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation |
Name: |
dwc_ucie_1ts4_tsmc3eff12_ns |
Version: |
1.10a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes Synopsys PHY IP UCIe CoWoS-S Interposer using 3DIC-Compiler Design Guidelines (Version 0.80a) ( PDF | HTML )
Synopsys PHY IP UCIe Signal Integrity and Power Integrity Training Guide Application Note (Version 0.50a) ( PDF | HTML )
Databooks Synopsys PHY IP Universal Chiplet Interconnect Express (UCIe) Standard Package PHY Utility Block (PUB) Databook (PUB Version 1.01a_d1) ( PDF | HTML )
Synopsys PHY IP Universal Chiplet Interconnect Express - Standard Package (UCIe-S) PHY for TSMC3EFF Databook (PHY Version: 1.00a) ( PDF | HTML )
Synopsys PHY IP Universal Chiplet Interconnect Express - Standard Package (UCIe-S) PHY for TSMC3EFF Databook (PHY Version: 1.10a) ( PDF | HTML )
Implementation Guide Synopsys PHY IP Universal Chiplet Interconnect Express - Standard Package (UCIe-S) PHY Implementation Guide (Version 1.30a) ( PDF | HTML )
Programming Guide Synopsys PHY IP Universal Chiplet Interconnect Express (UCIe) PHY Programming Guide (Version 0.80a) ( PDF | HTML )
Release Notes Synopsys PHY IP Universal Chiplet Interconnect Express - Standard Package (UCIe-S) PHY for TSMC3EFF Release Notes (PHY Version: 1.00a) ( TEXT )
Synopsys PHY IP Universal Chiplet Interconnect Express - Standard Package (UCIe-S) PHY for TSMC3EFF Release Notes (PHY Version: 1.10a) ( TEXT )
|
Download: |
dwc_ucie_1ts4_tsmc3eff12_ns |
Product Code: |
H735-0 |