Synopsys' DesignWare USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the leading process technologies to 5nm. Both the USB-C 3.1 and USB 3.1 PHYs use a single efficient GDSII design that supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes. To maximize battery life in mobile applications, the DesignWare USB-C/USB 3.1 PHYs are designed to minimize power consumption and standby current. In addition, the DesignWare USB-C 3.1 femtoPHY is optimized to support the USB Type-C connectivity specification.
Industry’s first PHY IP to support Type-C connectivity, the DesignWare USB/USB-C 3.1 PHYs, offer clear margins at 10 Gbps USB 3.1 throughput.
Synopsys DesignWare USB IP is the most certified USB IP solution in the industry. With over 3,000 design wins and approximately three billion silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHYs, verification IP, IP Prototyping Kits and IP software development kits, enables designers to lower integration risk and speed time-to-market.
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Highlights
Products
Downloads and Documentation
Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
USB-C 3.1 PHY IP supports USB Type-C specification
Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD
Design minimizes area and power
USB 3.1 PHY (10G/5G) - TSMC N3A x1 OTG, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
DesignWare Cores Consumer 10 USB 3.1 SS+ PHY ATE Test Bench for SS14LPP (PHY Version 1.03d) ( PDF ) DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores USB 3.1 SSP+ PHY for SS14LPP (PHY Version 1.03d) ( PDF | HTML ) USB 3.1 SuperSpeed Plus PCS for the DesignWare Cores USB 3.1 SuperSpeed Plus PHY for SS 14 LPP(1.03d) ( PDF | HTML )
Release Notes
DesignWare Cores USB 3.1 SS+ PHY for SS14LPP Release Notes (PHY Version 1.03d) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
DesignWare Cores USB 3.1 SSP+ PHY ATE Test Bench for GF22 (Doc Version: 1.60) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores Consumer 10G USB 3.1 SS+ PHY for GF22FDSOI x1 (PHY Version: 2.02a) ( PDF | HTML ) USB3.1SSP+ PCS for the DesignWare Cores USB3.1SSP+ PHY (PCS Version 3.2.6) ( PDF | HTML )
Release Notes
DesignWare Cores USB 3.1 SSP+ PHY x1 NS for GF22FDSOI 1.8V Release Notes (PHY Version: 2.02a) ( TEXT )
DesignWare Cores Consumer 10 USB 3.1 SS+ PHY ATE Test Bench for SS LPP ( PDF | HTML ) DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores USB 3.1 SS+ PHY for SS10LPP (PHY Version: 1.03c) ( PDF | HTML ) USB 3.1 SS+ PCS for the DesignWare Cores USB 3.1 SS+ PHY for SS LPP (1.00a) ( PDF | HTML )
DesignWare Cores Consumer 10 USB 3.1 SS+ PHY ATE Test Bench for SS1LPP x1 (PHY Version: 1.01c) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores USB 3.1 SSP+ PHY for SS11LPP x1 ( PDF | HTML ) USB 3.1 SSP PCS for the DesignWare Cores USB 3.1 SSP PHY for SS11LPP (1.01c) ( PDF | HTML )
Release Notes
DesignWare Cores USB 3.1 SSP+ PHY for SS11LPP Release Notes (PHY Version: 1.01c) ( TEXT )
DesignWare Cores Consumer 10 USB 3.1 SS+ PHY ATE Test Bench ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores USB 3.1 SS+ PHY for SS 8 LPP Databook (PHY Version: 1.00c) ( PDF | HTML ) USB 3.1 SSP PCS for the DesignWare Cores USB 3.1 SSP PHY for SS11LPP (1.01c) ( PDF | HTML )
Release Notes
DesignWare Cores USB 3.1 SS+ PHY for SS 8 LPP Release Notes (PHY Version: 1.00c) ( TEXT )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores USB 3.1 SS+ PHY Databook for Samsung 4LPE (PHY Version: 3.07a) ( PDF | HTML ) USB3.1SSP+ PCS for the DesignWare Cores USB3.1SSP+ PHY (PCS Version: 3.42a) ( PDF | HTML )
Release Notes
DesignWare Cores USB 3.1 SSP+ PHY for SS4LPE 1.2V (PHY Version: 3.07a) ( TEXT )
C10 Hardware Emulation Application Note ( PDF | HTML ) DesignWare Cores Consumer 10 USB 3.1 SS+ PHY ATE Test Bench for SS5LPE (Doc Version: 2.00a) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores Consumer 10G USB 3.1 SS+ PHY for SS5LPE Databook (PHY Version: 2.01g) ( PDF | HTML ) USB 3.1 SuperSpeed Plus PCS for the DesignWare Cores USB 3.1 SuperSpeed Plus PHY for SS5 LPE (PCS Version: 3.32a) ( PDF | HTML )
Release Notes
DesignWare Cores Consumer USB3.1 SSP+ PHY x1 NS for SS5LPE 1.8V Release Notes (PHY Version: 2.01g) ( TEXT )
DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF | HTML ) DesignWare® Cores USB 3.1 SS+ PHY ATE Test Bench ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores USB 3.1 SS+ PHY Databook for TSMC12FFC (PHY Version: 1.07a) ( PDF | HTML ) USB 3.1 SSP+ PCS for the DesignWare® Cores USB 3.1 SSP+ PHY (3.52a) ( PDF | HTML )
Release Notes
DesignWare Cores USB 3.1 SS+ PHY Release Notes for TSMC12FFC (PHY Version: 1.07a) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) USB 3.1 PHY Integration Review Checklist for TSMC16 FFPGL ( PDF )
Databooks
DesignWare Cores USB 3.1 SS+ PHY for TSMC 16 FFPGL ( PDF ) USB 3.1 SuperSpeed Plus PCS for the DesignWare Cores USB 3.1 SuperSpeed Plus PHY ( PDF )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Consumer 10 USB 3.1 SS+ PHY ATE Test Bench ( PDF ) DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) USB 3.1 PHY Integration Review Checklist for TSMC16 FFPLL ( PDF )
Databooks
DesignWare Cores USB 3.1 SS+ PHY for TSMC 16 FFPLL ( PDF ) USB 3.1 SuperSpeed Plus PCS for the DesignWare Cores USB 3.1 SuperSpeed Plus PHY ( PDF )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF | HTML ) DesignWare® Cores USB 3.1 SS+ PHY ATE Test Bench ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML ) USB 3.1 PHY Integration Review Checklist for TSMC16 FFC ( PDF )
Databooks
DesignWare Cores USB 3.1 SS+ PHY for TSMC16FFC Databook (PHY Version: 1.10a) ( PDF | HTML ) USB 3.1 SSP+ PCS for the DesignWare® Cores USB 3.1 SSP+ PHY (3.52a) ( PDF | HTML )
Release Notes
DesignWare Cores USB 3.1 SS+ PHY for TSMC16FFC Release Notes (PHY Version: 1.10a) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 1.00a) ( PDF | HTML ) Syopsys PHY IP USB 3.1 SSP+ PHY ATE Test Bench Application Note (Document Version: 2.20a) ( PDF | HTML )
Databooks
Synopsys PHY IP USB 3.1 SSP+ PCS PHY/PCS Wrapper Databook (PCS Version: 3.54d) ( PDF | HTML ) Synopsys PHY IP USB 3.1 SSP+ PHY for TSMC6FF Databook (PHY Version: 4.05a) ( PDF | HTML )
Reference Manual
Synopsys PHY IP USB 3.1 SSP+ PHY for TSMC6FF Reference Manual (PHY Version: 4.05a) ( PDF | HTML )
Release Notes
Synopsys PHY IP USB 3.1 SSP+ PHY for TSMC6FF Release Notes (PHY Version: 4.05a) ( TEXT )
DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 1.00a) ( PDF | HTML ) Syopsys PHY IP USB 3.1 SSP+ PHY ATE Test Bench Application Note (Document Version: 2.20a) ( PDF | HTML )
Databooks
Synopsys PHY IP USB 3.1 SS+ PHY for TSMC7FF Databook (PHY Version: 4.05a) ( PDF | HTML ) Synopsys PHY IP for the USB3.1 SSP+ PCS PHY/PCS Wrapper Databook (PCS Version: 3.54e) ( PDF | HTML )
Reference Manual
Synopsys PHY IP USB 3.1 SS+ PHY for TSMC7FF Reference Manual (PHY Version: 4.05a) ( PDF | HTML )
Release Notes
Synopsys PHY IP USB 3.1 SS+ PHY for TSMC7FF Release Notes (PHY Version: 4.05a) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys Compilation Using the LC and FC End-User Platform (Doc Version: 2022.03) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 2.00b) ( PDF | HTML ) Synopsys PHY IP USB 3.1 SSP+ PHY ATE Testbench Application Note (Document Version: 0.30a) ( PDF | HTML )
Databooks
Synopsys PHY IP USB 3.1 SSP+ PHY for TSMC N3P Databook (PHY Version: 4.50a) ( PDF | HTML ) USB 3.1 SSP+ PCS for the USB 3.1 SSP+ PHY (PCS Version: 2.08d) ( PDF | HTML )
Reference Manual
Synopsys PHY IP USB 3.1 SSP+ PHY for TSMC N3P Reference Manual (PHY Version: 4.50a) ( PDF | HTML )
Release Notes
Synopsys PHY IP USB 3.1 SSP+ PHY for TSMC N3P 1.2V Release Notes (PHY Version: 4.50a) ( TEXT )
User Guide
Synopsys PHY IP USB3.1 SSP+ PHY coreKit User Guide (Doc Version: 0.10d) ( PDF | HTML )
DesignWare Cores USB 3.1 SSP+ PHY ATE Test Bench (Doc Version: 1.90a) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores Consumer 10G USB 3.1 SSP+ PHY for TSMC5FF Databook (PHY Version: 4.01c) ( PDF | HTML ) USB3.1SSP+ PCS for the DesignWare Cores USB3.1SSP+ PHY (PCS Version: 3.55a) ( PDF | HTML )
Reference Manual
DesignWare Cores Consumer 10G USB 3.1 SSP+ PHY for TSMC5FF Reference Manual (PHY Version: 4.01a) ( PDF | HTML )
Release Notes
DWC USB3.1 SSP PHY x1 NS for TSMC5FF 1.2V Release Notes (PHY Version: 4.01c) ( TEXT )
DesignWare Cores Consumer 10 USB 3.1 SS+ PHY ATE Test Bench for SS5LPE (Doc Version: 2.00a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores USB 3.1 SSP+ PHY for SS5LPE (PHY Version: 2.04c) ( PDF | HTML ) USB 3.1 SuperSpeed Plus PCS for the DesignWare Cores USB 3.1 SuperSpeed Plus PHY (PCS Version: 3.23a) ( PDF ) USB 3.1 SuperSpeed Plus PCS for the DesignWare Cores USB 3.1 SuperSpeed Plus PHY for SS5 LPE (PCS Version: 3.23a) ( HTML )
Reference Manual
DesignWare Cores USB 3.1 SSP+ PHY for SS5LPE ( PDF | HTML )
Release Notes
DesignWare Cores USB 3.1 SSP+ PHY for SS5LPE Release Notes (PHY Version: 2.04c) ( TEXT )
SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML ) USBC 3.1 SS+ PHY ATE Test Bench (1.50a) ( HTML )
Databook
DesignWare Cores Type-C USB 3.1 SS+ PHY for TSMC12FFC Databook (PHY Version: 1.07a) ( PDF | HTML )
Release Notes
DesignWare Cores Type-C USB 3.1 SS+ PHY for TSMC12FFC Release Notes (PHY Version: 1.07a) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML ) USBC 3.1 SS+ PHY ATE Test Bench (1.50a) ( HTML )
Databooks
DesignWare Cores Type-C USB 3.1 SS+ PHY for TSMC16FFC Databook (PHY Version 1.10a) ( PDF | HTML ) USBC 3.1 SS+ PCS for the DesignWare Cores USBC 3.1 SS+ PHY (3.52a) ( PDF | HTML )
Release Notes
DesignWare Cores Type-C USB 3.1 SS+ PHY for TSMC16FFC Release Notes (PHY Version: 1.10a) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 1.00a) ( PDF | HTML ) Synopsys PHY IP USBC 3.1 SSP+ PHY ATE Test Bench (Doc Version: 1.60a) ( PDF | HTML )
Databooks
Synopsys PHY IP Type-C USB 3.1 SS+ PHY for TSMC6FF x1 (PHY Version: 4.05a) ( PDF | HTML ) Synopsys PHY IP Type-C USB3.1SSP+ PCS PHY/PCS Wrapper Databook (PCS Version: 3.54b) ( PDF | HTML )
Reference Manual
Synopsys PHY IP Type-C USB 3.1 SS+ PHY for TSMC6FF x1 Reference Manual (PHY Version: 4.05a) ( PDF | HTML )
Release Notes
Synopsys PHY IP Type-C USB 3.1 SS+ PHY for TSMC6FF Release Notes (PHY Ver: 4.05a) ( TEXT )
DesignWare Cores USBC 3.1 SSP+ PHY ATE Test Bench (Doc Version: 1.40a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores Type-C USB 3.1 SS+ PHY for TSMC7FF (PHY Version: 4.03a) ( PDF | HTML ) Type-C USB3.1SSP+ PCS for the DesignWare Cores Type-C USB3.1SSP+ PHY (PCS Version: 3.54a) ( PDF | HTML )
Release Notes
DesignWare Cores Type-C USB 3.1 SS+ PHY for TSMC7FF Release Notes (PHY Ver: 4.03a) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
DesignWare Cores USBC 3.1 SSP+ PHY ATE Test Bench (Doc Version: 1.40a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores Type-C USB3.1SS+ PHY Databook for TSMC5FF Databook (PHY Version: 4.01c) ( PDF | HTML ) Type-C USB3.1SSP+ PCS for the DesignWare Cores Type-C USB3.1SSP+ PHY (PCS Version: 3.55a) ( PDF | HTML )
Reference Manual
DesignWare Cores Type-C USB3.1SS+ PHY Databook for TSMC5FF Reference Manual (PHY Version: 4.01c) ( PDF | HTML )
Release Notes
DWC USBC3.1 SSP+ PHY NS for TSMC5FF 1.2V Release Notes (PHY Version: 4.01c) ( TEXT )
DesignWare Cores USBC 3.1 SSP+ PHY ATE Test Bench (Doc Version: 1.40a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
Synopsys PHY IP Type-C USB 3.1 SSP+ for TSMC5AFF Databook for Automotive Grade, Grade 2 (AG) (PHY Version: 4.12a_d1) ( PDF | HTML ) Synopsys PHY IP Type-C USB3.1SSP+ PCS PHY/PCS Wrapper Databook (PCS Version: 3.54b) ( PDF | HTML ) USBC3.1SSP+ PCS for the Synopsys PHY IP USBC3.1SSP+ PHY (PCS Version: 3.55c) ( PDF | HTML )
Reference Manual
Synopsys PHY IP Type-C USB 3.1 SSP+ for TSMC5AFF Reference Manual for Automotive Grade, Grade 2 (AG) (PHY Version: 4.12a) ( PDF | HTML )
Release Notes
Synopsys IP USBC3.1 SSP+ PHY x2 for TSMC5FF 1.2V Release Notes (PHY Version: 4.12a) ( TEXT )
DesignWare Cores Type-C USB 3.1 SS+ / DP Alt PHY ATE Test Bench for SS11LPP (PHY Version: 1.03b) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores Type-C USB 3.1 SS+ / DP Alt PHY for SS 11LPP (PHY Version: 1.03b) ( PDF | HTML ) Type-C USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C USB3.1SSP+ / DP Alt PHY for SS11LPP (1.03b) ( PDF | HTML )
Release Notes
Type-C USB 3.1 / DP PHY X4 NS for SS 11LPP 1.8V Release Notes (PHY Version: 1.03b) ( TEXT )
DesignWare Cores Consumer 10 Type-C USB 3.1 SS+ / DP Alt PHY ATE Test Bench (Doc version: 1.31) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores DP AUX PHY for SS14LPP 1.8 V ( PDF | HTML ) DesignWare Cores Type-C USB 3.1 SSP+ / DP Alt PHY for SS14LPP (PHY Version: 1.04c) ( PDF | HTML ) Type-C USB3.1SSP+ / DP Alt PCS for the DesignWare Type-C USB3.1SSP+ / DP Alt PHY for SS14LPP (1.04c) ( PDF | HTML )
Release Notes
Type-C USB 3.1 DPPHY x4 NS for SS14LPP 1.8V Release Notes (PHY Version: 1.04c) ( TEXT )
DesignWare Cores Consumer Type-C USB3.1SS+/DP Alt PHY ATE Test Bench (Version: 1.50a) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores DP AUX PHY for TSMC 12FFC (PHY Version: 1.07a) ( PDF | HTML ) Synopsys PHY IP Type-C USB 3.1 SS+ / DP Alt PHY for TSMC 12FFC (PHY Version: 1.07a_d2) ( PDF | HTML ) Type-C - USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C - USB3.1SSP+ / DP Alt PHY for TSMC12FFC (1.07a) ( PDF | HTML )
Release Notes
Type-C USB 3.1 DP PHY x4 NS for TSMC 12FFC 1.8V Release Notes (1.07a) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
DP AUX/AUX-I2C PHY INTEGRATION REVIEW CHECKLIST for TSMC16FFC (1.0) ( PDF ) DesignWare Cores Consumer Type-C USB3.1SS+/DP Alt PHY ATE Test Bench (Version: 1.50a) ( PDF | HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML ) USB 3.1/DP Alt PHY Integration Review Checklist for TSMC16 FFC ( PDF )
Databooks
DesignWare Cores DP AUX PHY for TSMC16FFC (PHY Version: 1.10a) ( PDF | HTML ) DesignWare Cores Type-C USB 3.1 SS+ / DP Alt PHY X4 for TSMC 16FFC (PHY Version: 1.10a_d1) ( PDF | HTML ) USBC 3.1 SS+ PCS for the DesignWare Cores USBC 3.1 SS+ PHY (3.52a) ( PDF | HTML )
Release Notes
Type-C USB3.1 SS+ / DP Alt PHY x4 for TSMC 16FFC Release Notes (PHY Version: 1.10a) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF | HTML ) Synopsys PHY IP Consumer 10G Type-C USB 3.1 DP PHY ATE Testbench Application Note (Doc Version: 1.90b) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 1.00a) ( PDF | HTML )
Databooks
Synopsys PHY IP DP AUX-I2C PHY for TSMC7FF 1.8 V (PHY Version: 4.05a) ( PDF | HTML ) Synopsys PHY IP Type-C USB 3.1SSP+ / DP Alt PHY for TSMC7FF Databook (PHY Version: 4.05a) ( PDF | HTML ) Synopsys PHY IP Type-C USB3.1SSP+ / DP Alt PCS PHY/PCS Wrapper Databook (PCS Version: 3.54c) ( PDF | HTML )
Reference Manual
Synopsys PHY IP Type-C USB 3.1SSP+ / DP Alt PHY for TSMC7FF Reference Manual (PHY Version: 4.05a) ( PDF | HTML )
Release Notes
Synopsys PHY IP Type-C USB 3.1SSP+ / DP Alt PHY for TSMC7FF Release Notes (PHY Version: 4.05a) ( TEXT )
White Papers
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
DesignWare Cores Type-C USB 3.1 DP PHY ATE Test Bench (Doc Version: 1.71a) ( PDF | HTML ) High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML ) Synopsys Compilation Using the LC and FC End-User Platform (Doc Version: 2022.03) ( PDF | HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks
DesignWare Cores DP AUX-I2C PHY for Automotive (AG) TSMC7FF 1.8V (PHY Version: 4.03d) ( PDF | HTML ) Synopsys PHY IP Type-C USB3.1 SSP+ / DP Alt PHY for Automotive Grade 2 TSMC7FF (PHY Version: 4.03d) ( PDF | HTML ) Type-C USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C - USB3.1SSP+ / DP Alt PHY (PCS Version: 3.52g) ( PDF | HTML )
Reference Manual
Synopsys PHY IP Type-C USB3.1 SSP+ / DP Alt PHY for Automotive Grade 2 TSMC7FF Reference Manual (PHY Version: 4.03d) ( PDF | HTML )
Release Notes
DesignWare Cores Type-C USB3.1/DP PHY NS for TSMC7FF 1.8V Release Notes (PHY Version: 4.03d) ( TEXT )
DesignWare SuperSpeed USB 3.1 IP Solution
