Synopsys XHC & XBC OTP NVM IP: SHF Architecture

The Synopsys XHC/XBC One Time Programmable (OTP) Non-Volatile Memory (NVM) IP, based on the SHF architecture, employs a patented antiFuse bitcell operating on gate oxide breakdown as a programming mechanism. The IP can be manufactured without any additional masks or process steps, making it cost effective, reliable, and scalable. The bitcell is intrinsically secure, making it virtually impossible to distinguish between programmed and unprogrammed locations upon visual inspection.

To serve a wide range of applications, the SHF architecture features optimal area and performance with low power consumption. The IP provides an alternative to mask ROM, eFuses, and Flash memory in many applications.

The SHF architecture is designed for ease-of-integration into an SoC with multiple options and read modes to trade off area, speed, and power.

The OTP NVM IP memory array is delivered as a hard macro. An integrated power supply consisting of the voltage regulators and a high-voltage charge pump for programming is delivered as an optional hard macro. The OTP NVM IP controller enabling BIST, ECC, and repair is delivered as an optional soft macro. Production test flow is simplified by the OTP NVM IP controller.

Programming options include single and multi-bit. Multi-bit programming is facilitated by an external power supply. Only bits intended as 1s must be programmed. Unprogrammed bits remain 0s.

The SHF architecture’s reliability is qualified to meet or exceed 10 years data retention per JEDEC/JESD standards for continuous operation at the maximum specified operating temperature. Characterization of skewed silicon material assures the specified performance parameters. SHF has also been Automotive-Grade AEC-Q100 qualified on select process geometries.

Synopsys SHF OTP NVM IP Datasheet