Synopsys XBC OTP NVM IP: SiPROM Architecture

The Synopsys XBC One Time Programmable (OTP) Non-Volatile Memory (NVM) IP, based on the SiPROM architecture, employs a patented antiFuse bitcell operating on gate oxide breakdown as a programming mechanism. The IP can be manufactured without any additional masks or process steps, making it cost effective, reliable, and scalable. The bitcell is intrinsically secure making it virtually impossible to distinguish between programmed and unprogrammed locations upon visual inspection.

To serve a wide range of applications, the SiPROM architecture features optimized area for fast reads, with low power consumption, and provides an alternative to mask ROM, eFuses and Flash memory in many applications.

The SiPROM architecture is designed for ease-of-integration into an SoC with multiple options and read modes to trade off area, speed, and power.

The OTP NVM IP is delivered as a single hard macro with embedded voltage regulators and a high voltage charge pump for programming. No external voltages need to be supplied except for power.

Programming options include single and multi-bit. Single bit programming is supported with the embedded charge pump or an external supply. Multi-bit programming is facilitated by an external power supply. Only bits intended as 1s must be programmed. Unprogrammed bits remain 0s.

The SiPROM architecture reliability is qualified to meet or exceed 10 years data retention per JEDEC/JESD standards for continuous operation at the maximum specified operating temperature. Characterization of skewed silicon material assures the specified performance parameters.

Synopsys XBC OTP NVM IP - SiPROM Architecture